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datasheet 3 document #: 248987 revision#: 003 rev date: 08/07/01 advanced 10/100 repeater with integrated management ? lxt9860/9880 contents 1.0 other related documents ? .......................................................................................... 11 2.0 pin assignments and signal descriptions .................................................................. 12 3.0 functional description .................................................................................................. 31 3.1 introduction.......................................................................................................... 31 3.2 port configuration ............................................................................................... 32 3.2.1 auto-negotiation..................................................................................... 32 3.2.2 forced operation ................................................................................... 33 3.2.3 changing port speed - forced............................................................... 33 3.2.4 link establishment and port connection ............................................... 33 3.2.5 mii port configuration ............................................................................ 33 3.3 interface descriptions.......................................................................................... 33 3.3.1 twisted-pair interface ............................................................................ 33 3.3.2 media independent interface.................................................................. 34 3.3.3 serial management interface ................................................................. 34 3.3.4 serial prom interface ........................................................................... 35 3.4 repeater operation............................................................................................. 35 3.4.1 100 mbps repeater operation ............................................................... 35 3.4.2 10 mbps repeater operation ................................................................. 36 3.5 management support.......................................................................................... 37 3.5.1 configuration and status........................................................................ 37 3.5.2 snmp and rmon support .................................................................... 37 3.5.3 source address management................................................................ 37 3.6 requirements ...................................................................................................... 37 3.6.1 power ..................................................................................................... 37 3.6.2 clock ...................................................................................................... 38 3.6.3 bias resistor .......................................................................................... 38 3.6.4 reset ...................................................................................................... 38 3.6.5 prom..................................................................................................... 38 3.6.6 chip id ................................................................................................... 38 3.6.7 management master i/o link ................................................................. 38 3.6.8 irb bus pull-ups .................................................................................... 38 3.7 led operation..................................................................................................... 39 3.7.1 leds at start-up..................................................................................... 39 3.7.2 led event stretching ............................................................................. 39 3.7.3 led blink rates ..................................................................................... 39 3.7.4 serial led interface ............................................................................... 40 3.7.4.1 serial shifting ............................................................................ 40 3.7.4.2 serial led signals .................................................................... 40 3.7.4.3 activity graph leds .................................................................. 41 3.7.5 direct drive leds................................................................................... 42 3.7.6 led modes............................................................................................. 42 3.7.6.1 led mode 1 .............................................................................. 44 3.7.6.2 led mode 2 .............................................................................. 45 3.7.6.3 led mode 3 .............................................................................. 46 3.7.6.4 led mode 4 .............................................................................. 47
lxt9860/9880 ? advanced 10/100 repeater with integrated management 4 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.8 irb operation ..................................................................................................... 47 3.8.1 irb signal types ................................................................................... 48 3.8.2 irb isolation ........................................................................................... 48 3.8.3 10 mbps-only operation ........................................................................ 48 3.8.3.1 mac irb access....................................................................... 48 3.8.3.2 management master chain arbitration...................................... 48 3.8.4 lxt98x/91x/98x0 compatibility.............................................................. 48 3.9 mii port operation............................................................................................... 51 3.9.1 preamble handling................................................................................. 51 3.10 serial management i/f........................................................................................ 52 3.10.1 smi signals ............................................................................................ 52 3.10.1.1serial clock ............................................................................... 53 3.10.1.2serial data i/o........................................................................... 53 3.10.2 read and write operations.................................................................... 53 3.10.2.1smi collision handling .............................................................. 53 3.10.2.2smi address match indication .................................................. 53 3.10.2.3smi frame format .................................................................... 54 3.10.3 address assignment methods ............................................................... 57 3.10.3.1chain arbitration mechanism .................................................... 58 3.10.3.2prom arbitration mechanism................................................... 58 3.10.3.3address re-arbitration .............................................................. 59 3.10.4 interrupt functions ................................................................................. 59 3.11 serial prom interface ........................................................................................ 59 3.12 serial configuration interface.............................................................................. 60 4.0 application information ................................................................................................. 61 4.1 general design guidelines ................................................................................. 61 4.2 typical applications ............................................................................................ 62 4.3 application circuitry ............................................................................................ 63 4.3.1 power and ground ................................................................................. 63 4.3.1.1 supply filtering.......................................................................... 63 4.3.1.2 ground noise ............................................................................ 63 4.3.1.3 power and ground plane layout considerations ..................... 63 4.3.1.4 chassis ground......................................................................... 64 4.3.1.5 the rbias pin .......................................................................... 64 4.3.2 mii terminations .................................................................................... 65 4.3.3 twisted-pair interface ............................................................................ 65 4.3.3.1 magnetics information ............................................................... 66 4.3.4 clock ...................................................................................................... 66 4.3.5 smi and prom circuits ......................................................................... 68 4.3.6 led circuits ........................................................................................... 69 4.3.6.1 direct drive leds...................................................................... 69 4.3.6.2 led pins multiplexed with configuration inputs........................ 69 4.3.6.3 serial leds ............................................................................... 70 4.4 inter-repeater backplane compatibility.............................................................. 71 4.4.1 local backplane ? 3.3v only ................................................................. 72 4.4.2 stack backplane ? 3.3v or 5v ................................................................ 72 4.4.2.1 3.3v and 5.0v stacking boards cannot be mixed.................... 72
datasheet 5 document #: 248987 revision#: 003 rev date: 08/07/01 advanced 10/100 repeater with integrated management ? lxt9860/9880 5.0 test specifications ......................................................................................................... 75 6.0 register definitions ....................................................................................................... 87 6.1 register map ....................................................................................................... 87 6.2 counter registers ............................................................................................... 95 6.2.1 port counter registers........................................................................... 95 6.2.2 rmon counter registers ...................................................................... 96 6.3 ethernet address registers ................................................................................ 99 6.3.1 port address registers .......................................................................... 99 6.3.2 search address registers...................................................................... 99 6.4 repeater port control registers .......................................................................101 6.4.1 general port control registers ............................................................101 6.4.2 port link control register ....................................................................101 6.4.3 port learn enable register ..................................................................102 6.5 repeater port status registers.........................................................................102 6.6 phy port status registers ................................................................................104 6.7 phy port control registers...............................................................................107 6.8 repeater port control/status registers ............................................................108 6.8.1 device/revision register .....................................................................111 6.8.2 led control registers.......................................................................... 111 6.8.3 led global control register ................................................................ 111 6.8.4 port led control register....................................................................111 6.8.5 led timer control register .................................................................112 6.8.6 repeater reset register......................................................................113 6.8.7 software reset register ......................................................................113 6.8.8 interrupt registers................................................................................113 6.9 serial controller registers ................................................................................115 7.0 mechanical specifications ...........................................................................................117
lxt9860/9880 ? advanced 10/100 repeater with integrated management 6 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 figures 1 lxt98x0 block diagram ..................................................................................... 11 2 lxt98x0 pin assignments .................................................................................. 12 3 typical lxt988x managed repeater architectures ........................................... 32 4 mii interface ........................................................................................................ 34 5 led blink rates .................................................................................................. 39 6 serial led shift loading .................................................................................... 40 7 serial led port signaling.................................................................................... 41 8 100 mbps irb connection .................................................................................. 49 9 irb block diagram ............................................................................................. 50 10 lxt9880 mii operation....................................................................................... 52 11 typical smi bus architecture ............................................................................. 52 12 smi collision handling ........................................................................................ 54 13 smi address match indication ............................................................................ 54 14 serial management frame format ..................................................................... 55 15 address arbitration mechanisms ....................................................................... 58 16 optional r/w serial prom interface.................................................................. 60 17 serial configuration interface.............................................................................. 61 18 serial configuration interface signaling.............................................................. 61 19 8-port managed 10/100 stackable repeater...................................................... 62 20 32-port managed 10/100 repeater..................................................................... 62 21 power and ground connections ......................................................................... 65 22 typical twisted-pair port interface and power supply filtering ........................ 67 23 typical serial management interface connections............................................. 68 24 serial controller connection showing pal......................................................... 68 25 serial prom interface ........................................................................................ 69 26 typical reset circuit .......................................................................................... 69 27 led circuits - direct drive & multiplexed configuration inputs .......................... 70 28 serial led circuit................................................................................................ 71 29 100 mbps backplane connection between lxt98x and lxt98x0 ..................... 73 30 typical 100 mbps irb implementation ............................................................... 74 31 typical 10 mbps irb implementation ................................................................ 74 32 100 mbps tp port-to-port delay timing ............................................................. 79 33 100base-tx mii-to-tp port timing ................................................................... 80 34 100base-tx tp-to-mii timing ........................................................................... 81 35 10base-t mii-to-tp timing ............................................................................... 82 36 10base-t tp-to-mii timing ............................................................................... 83 37 100 mbps tp-to-irb timing................................................................................ 84 38 10 mbps tp-to-irb timing.................................................................................. 84 39 10 mbps irb-to-tp port timing .......................................................................... 85 40 serial management interface timing .................................................................. 86 41 prom interface timing....................................................................................... 87 42 lxt98x0 package specifications for commercial temperature....................... 117 43 lxt98x0 package specifications for extended temperature........................... 118
datasheet 7 document #: 248987 revision#: 003 rev date: 08/07/01 advanced 10/100 repeater with integrated management ? lxt9860/9880 tables 1 signal types........................................................................................................ 13 2 lxt98x0 pins, numeric order ............................................................................ 13 3 mii #1 signal descriptions................................................................................... 20 4 mii #2 signal descriptions................................................................................... 21 5 inter-repeater backplane signal descriptions.................................................... 22 6 twisted-pair port signal descriptions ................................................................. 25 7 serial management interface signal descriptions .............................................. 26 8 led signal descriptions...................................................................................... 27 9 power supply and indication signal descriptions ............................................... 28 10 prom interface signal descriptions................................................................... 29 11 miscellaneous signal descriptions...................................................................... 30 12 serial led port bit stream.................................................................................. 41 13 actgled display modes................................................................................... 42 14 led terms .......................................................................................................... 43 15 led mode 1 indications ...................................................................................... 44 16 led mode 2 indications ...................................................................................... 45 17 led mode 3 indications ...................................................................................... 46 18 led mode 4 indications ...................................................................................... 47 19 cascading and stacking connections................................................................. 50 20 irb signal details ............................................................................................... 51 21 smi message fields............................................................................................ 55 22 smi header storage............................................................................................ 55 23 smi command set .............................................................................................. 56 24 typical serial management packets ................................................................... 57 25 lxt98x0 magnetics specifications ..................................................................... 66 26 oscillator manufacturers ..................................................................................... 67 27 absolute maximum ratings................................................................................. 75 28 operating conditions........................................................................................... 75 29 input system clock1 requirements .................................................................... 75 30 i/o electrical characteristics ............................................................................... 76 31 100 mbps irb electrical characteristics ............................................................. 76 32 10 mbps irb electrical characteristics ............................................................... 77 33 100base-tx transceiver electrical characteristics........................................... 78 34 10base-t transceiver electrical characteristics ............................................... 78 35 100 mbps tp port-to-port delay timing parameters.......................................... 79 36 100base-tx mii-to-tp port timing parameters ................................................ 80 37 100base-tx tp-to-mii timing parameters........................................................ 81 38 10base-t mii-to-tp timing parameters ............................................................ 82 39 10base-t tp-to-mii timing parameters ............................................................ 83 40 100 mbps tp-to-irb timing parameters 1 ................................................................................84 41 10 mbps tp-to-irb timing parameters 1...................................................................................85 42 10 mbps irb-to-tp port timing parameters....................................................... 86 43 serial management interface timing characteristics.......................................... 86 44 prom interface timing characteristics .............................................................. 87 45 register map ....................................................................................................... 88 46 port counter registers........................................................................................ 95 47 rmon counter registers - 10 mbps .................................................................. 97 48 rmon counter registers - 100 mbps ................................................................ 98 49 ethernet address register bit assignments ....................................................... 99
lxt9860/9880 ? advanced 10/100 repeater with integrated management 8 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 50 port address tracking registers ........................................................................ 99 51 search address/search address match register ............................................. 100 52 search address register bit assignments ....................................................... 100 53 search match address bit assignments ........................................................... 100 54 search match address bit definitions............................................................... 100 55 port control register bit assignments .............................................................. 101 56 general port control registers ......................................................................... 101 57 port link control and status register bit assignments .................................... 101 58 port link control register ................................................................................. 102 59 port learn enable register............................................................................... 102 60 port learn enable register............................................................................... 102 61 port status register bit assignments ............................................................... 103 62 port status registers ........................................................................................ 103 63 mii speed status bit assignments .................................................................... 103 64 mii status bit definitions ................................................................................... 103 65 auto-negotiation registers ............................................................................... 104 66 auto-negotiate link partner advertisement bit definitions............................... 104 67 auto-negotiate expansion bit definitions ......................................................... 105 68 phy port status register summary ................................................................. 105 69 phy port status register bit definitions........................................................... 106 70 auto-negotiation advertisement registers ....................................................... 107 71 auto negotiate advertisement bit definitions ................................................... 107 72 phy port control register ................................................................................ 107 73 phy port control bit definitions........................................................................ 108 74 configuration registers..................................................................................... 108 75 repeater configuration register....................................................................... 109 76 repeater serial configuration........................................................................... 110 77 device/revision register bit assignment ......................................................... 111 78 global fault led bit assignments .................................................................... 111 79 .......................................................................................................................... 111 80 led configuration............................................................................................. 112 81 port led1, 2, 3 control encodings ................................................................... 112 82 led timer control register bit assignments ................................................... 112 83 repeater reset ................................................................................................. 113 84 software reset.................................................................................................. 113 85 interrupt status/mask register.......................................................................... 113 86 interrupt status register bit definitions ............................................................ 114 87 interrupt mask bit definitions ............................................................................ 115 88 configuration registers..................................................................................... 115 89 assign addr 1.................................................................................................... 115 90 assign addr 2.................................................................................................... 116 91 prom addr 1.................................................................................................... 116 92 prom addr 2.................................................................................................... 116
datasheet 9 document #: 248987 revision#: 003 rev date: 08/07/01 advanced 10/100 repeater with integrated management ? lxt9860/9880 revision history date revision page description august 2001 003 75 changed absolute maximum ratings supply voltage value to 4.0v. january 2001 002 title page added extended temperature range to title page. 13 modified lxt98x0 pins, numeric order table (pins 10, 11, 17, 19, 20, 185. 38 modified clock requirements language. 38 replaced tbd with 3.15v under reset. 65 under twisted pair interface, 4th bullet: replaced text containingt- bds with: a ferrite bead with a total maximum current rating of 1.5amp is recommended. 67 modified oscillator manufacturers table. 75 modified absolute maximum ratings table. 75 modified operating conditions table. 117 , 118 mechanical specifications: add part number lxt98x0ahc to lxt98x0 package specifications commercial temperature figure; add page for lxt98x0 package specifications extended tempera- ture figure.

advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 11 1.0 other related documents ? the lxt98x0 design and layout guide (formerly application note 113) provides detailed design and layout guidelines. the irb design and layout guide (formerly application note 112) provides detailed guidelines design and layout of intel ? s inter-repeater backplane (irb). the lxt98x-to-lxt98x0 migration guide (formerly application note 111) compares features and registers of the lxt98x and more recent lxt98x0 devices. the lxt9883/lxt9863 data sheet specifically details the unmanaged eight-port and six-port devices. the high-speed serial management interface (formerly application note 64) explains how to connect an scc to intel devices and how to implement management across a network system. figure 1. lxt98x0 block diagram 10base-t repeater 100base-x repeater serial led drivers 10/100 phy 1 rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port device management port switching logic 10m irb 100m irb mode control serial mgmt port & mgmt status indicators tx_i/o 10/100 phy 2 tx_i/o 10/100 phy 3 tx_i/o 10/100 phy 4 tx_i/o 10/100 phy 5 tx_i/o 10/100 phy 6 tx_i/o 10/100 phy 7 tx_i/o 10/100 phy 8 tx_i/o mii 1 mii_i/o mii 2 mii_i/o
lxt9860/9880 ? advanced 10/100 repeater with integrated management 12 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 2.0 pin assignments and signal descriptions figure 2. lxt98x0 pin assignments reset ....... 53 clk25....... 54 ir10iso ....... 55 ir100iso ....... 56 reconfig ....... 57 srx ....... 58 stx ....... 59 serclk ....... 60 vcc ....... 61 gnd....... 62 ser_match....... 63 mmstrout....... 64 arbout....... 65 n/c....... 66 mgr_pres ....... 67 prom_clk ....... 68 prom_cs ....... 69 prom_dtout....... 70 prom_dtin ....... 71 chipid0 ....... 72 chipid1 ....... 73 vcc ....... 74 gnd....... 75 vcc ....... 76 vcc ....... 77 rps_fault ....... 78 rps_pres ....... 79 macactive ....... 80 holdcol ....... 81 ledclk/cfg_clk ...82 leddat ....... 83 ledlat ....... 84 vcc ....... 85 gnd....... 86 port1_led3....... 87 port1_led2....... 88 port1_led1....... 89 gnd....... 90 port2_led3....... 91 port2_led2....... 92 port2_led1....... 93 gnd....... 94 port3_led3....... 95 port3_led2....... 96 port3_led1....... 97 gnd....... 98 port4_led3....... 99 port4_led2....... 100 port4_led1....... 101 rbias ....... 102 gnd....... 103 tpip1....... 104 208........mii2_rxd3 207........mii2_rxd2 206........mii2_rxd1 205........mii2_rxd0 204........mii2_rxdv 203........mii2_rxclk 202........mii2_rxer 201........mmstrin 200........vcc 199........gnd 198........arbin 197........mii2_txer 196........mii2_txclk 195........mii2_txen 194........mii2_txd0 193........mii2_txd1 192........mii2_txd2 191........mii2_txd3 190........vcc 189........gnd 188........mii2_col 187........mii2_crs 186........arbselect/col100_led 185........ledsel1/col10_led 184........ledsel0/act100_led 183........ autoblink /act10_led 182........ irq 181........gnd 180........vcc 179........gnd 178........n/c 177........vcc 176........port8_led1* 175........port8_led2*/ledabgsel 174......... port8_led3* 173........vcc 172........gnd 171........port7_led1* 170........port7_led2* 169........port7_led3* 168........gnd 167........port6_led1 166........port6_led2 165........port6_led3 164........gnd 163........port5_led1 162........port5_led2 161........port5_led3 160........txslew_1 159........txslew_0 158......... gnd 157........*tpip8 tpin1....... 105 vccr....... 106 tpop1....... 107 tpon1....... 108 gnd....... 109 tpon2....... 110 tpop2....... 111 vcct ....... 112 vccr....... 113 tpin2....... 114 tpip2....... 115 gnd....... 116 gnd....... 117 tpip3....... 118 tpin3....... 119 vccr....... 120 tpop3....... 121 tpon3....... 122 gnd....... 123 tpon4....... 124 tpop4....... 125 vcct ....... 126 vccr....... 127 tpin4....... 128 tpip4....... 129 gnd....... 130 gnd....... 131 tpip5....... 132 tpin5....... 133 vccr....... 134 vcct ....... 135 tpop5....... 136 tpon5....... 137 gnd....... 138 tpon6....... 139 tpop6....... 140 vccr....... 141 tpin6....... 142 tpip6....... 143 gnd....... 144 gnd....... 145 * tpip7....... 146 * tpin7....... 147 vccr....... 148 vcct ....... 149 * tpop7....... 150 * tpon7....... 151 gnd....... 152 * tpon8....... 153 * tpop8....... 154 vccr....... 155 * tpin8....... 156 * indicates lxt9880-only pins. tp ports 7 and 8 are not available on lxt9860 devices. 52 .......... nc 51 .......... nc 50 .......... ir100clk 49 .......... ir100dat4 48 .......... ir100dat3 47 .......... vcc 46 .......... gnd 45 .......... ir100dat2 44 .......... ir100dat1 43 .......... ir100dat0 42 .......... ir100dv 41 .......... ir100den 40 .......... ir100col 39 .......... comp_sel 38 .......... ir100sngl 37 .......... ir100cfsbp 36 .......... ir100cfs 35 .......... mii1_rxd3 34 .......... mii1_rxd2 33 .......... config0/cfg_dt 32 ......... mii1_rxd1 31 .......... mii1_rxd0 30 .......... mii1_rxdv 29 .......... mii1_rxclk 28 .......... vcc 27 .......... gnd 26 .......... mii1_rxer 25 .......... config1/cfg_ld 24 .......... mii1_txer 23 .......... mii1_txclk 22 .......... mii1_txen 21 .......... mii1_txd0 20 .......... mii1_txd1 19 .......... mii1_txd2 18 .......... mii2_spd 17 .......... mii1_txd3 16 .......... vcc 15 .......... gnd 14 .......... mii1_col 13 .......... mii1_crs 12 .......... ir10clk 11 .......... ir10dat 10 .......... ir10ena 9 ............ mii1_spd 8 ............ vcc 7 ............ gnd 6 ............ ir10den 5 ............ ir10cfsbp 4 ............ ir10colbp 3 ............ ir10col 2 ............ ir10cfs 1 ............ gnd lxt98x0 xx xxxxxx xxxxxxxx part # lot # fpo # rev #
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 13 table 1. signal types type name definition i input standard input-only signal. o output standard output-only signal. i/o bidirectional input and output signal. a analog current source signal. od open drain output that will only drive the signal low. os open source output that will only drive the signal high. pd pull down internal, weak pull down signal. pu pull up internal, weak pull up signal. nc no clamp pad does not clamp input in the absence of power. table 2. lxt98x0 pins, numeric order pin symbol type 1,2 reference for full description 1. gnd - table 9 on page 28 2. ir10cfs a, i/o, od table 5 on page 22 3. ir10col i/o, od, pu table 5 on page 22 4. ir10colbp i/o, od table 5 on page 22 5. ir10cfsbp a i/o, od table 5 on page 22 6. ir10den o, od table 5 on page 22 7. gnd - table 9 on page 28 8. vcc - table 9 on page 28 9. mii1_spd i, pu table 3 on page 20 10. ir10ena o, table 3 on page 20 11. ir10dat o table 3 on page 20 12. ir10clk i/o table 5 on page 22 13. mii1_crs o table 3 on page 20 14. mii1_col o table 3 on page 20 15. gnd - table 9 on page 28 16. vcc - table 9 on page 28 17. mii1_txd3 i table 3 on page 20 18. mii2_spd i table 3 on page 20 19. mii1_txd2 i table 3 on page 20 20. mii1_txd1 i table 3 on page 20 21. mii1_txd0 i table 3 on page 20 1. refer to table 1 for signal type definitions. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 14 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 22. mii1_txen i table 3 on page 20 23. mii1_txclk i table 3 on page 20 24. mii1_txer i table 3 on page 20 25. config1/cf i/o table 11 on page 30 26. mii1rxer i table 3 on page 20 27. gnd - table 9 on page 28 28. vcc - table 9 on page 28 29. mii1_rxclk o table 3 on page 20 30. mii1_rxdv o table 3 on page 20 31. mii1_rxd0 o table 3 on page 20 32. mii1_rxd1 o table 3 on page 20 33. config/cfg_dt i table 12 on page 41 34. mii1_rxd2 o table 3 on page 20 35. mii1_rxd3 o table 3 on page 20 36. ir100cfs a i/o table 5 on page 22 37. ir100cfsbp a i/o table 5 on page 22 38. ir100sngl i/o table 5 on page 22 39. comp_sel ai table 5 on page 22 40. ir100col o table 5 on page 22 41. ir100den o table 5 on page 22 42. ir100dv i/o table 5 on page 22 43. ir100dat0 i/o table 5 on page 22 44. ir100dat1 i/o table 5 on page 22 45. ir100dat2 i/o table 5 on page 22 46. gnd - table 9 on page 28 47. vcc - table 9 on page 28 48. ir100dat3 i/o table 5 on page 22 49. ir100dat4 i/o table 5 on page 22 50. ir100clk i/o table 5 on page 22 51. nc - table 11 on page 30 52. nc - table 11 on page 30 53. reset i table 11 on page 30 54. clk25 i table 11 on page 30 55. ir10iso o table 5 on page 22 table 2. lxt98x0 pins, numeric order pin symbol type 1,2 reference for full description 1. refer to table 1 for signal type definitions. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 15 56. ir100iso o table 5 on page 22 57. reconfig i, pd table 7 on page 26 58. srx i, pd table 7 on page 26 59. stx o, od table 7 on page 26 60. serclk i/o, tri-state, pd table 7 on page 26 61. vcc - table 9 on page 28 62. gnd table 9 on page 28 63. ser_match o table 7 on page 26 64. mmstrout o table 5 on page 22 65. arbout o table 7 on page 26 66. nc - table 11 on page 30 67. mgr_pres i pu table 7 on page 26 68. prom_clk i/o tri-state pd table 10 on page 29 69. prom_cs o, tri-state table 10 on page 29 70. prom_dtout o, tri-state table 10 on page 29 71. prom_dtin i, pd table 10 on page 29 72. chipid0 i pd table 11 on page 30 73. chipid1 i pd table 11 on page 30 74. vcc - table 9 on page 28 75. gnd - table 9 on page 28 76. vcc - table 9 on page 28 77. vcc - table 9 on page 28 78. rps_fault i, pu table 9 on page 28 79. rps_pres i, pu table 9 on page 28 80. macactive i, pd table 5 on page 22 81. holdcol i/o, pd table 5 on page 22 82. ledclk cfg_clk o table 8 on page 27 83. leddat o table 8 on page 27 84. ledlat o table 8 on page 27 85. vcc - table 9 on page 28 table 2. lxt98x0 pins, numeric order pin symbol type 1,2 reference for full description 1. refer to table 1 for signal type definitions. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 16 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 86. gnd - table 9 on page 28 87. port1_led3 o, od table 8 on page 27 88. port1_led2 o, od table 8 on page 27 89. port1_led1 o, od table 8 on page 27 90. gnd - table 9 on page 28 91. port2_led3 o, od table 8 on page 27 92. port2_led2 o, od table 8 on page 27 93. port2_led1 o, od table 8 on page 27 94. gnd - table 9 on page 28 95. port3_led3 o, od table 8 on page 27 96. port3_led2 o, od table 8 on page 27 97. port3_led1 o, od table 8 on page 27 98. gnd - table 9 on page 28 99. port4_led3 o, od table 8 on page 27 100. port4_led2 o, od table 8 on page 27 101. port4_led1 o, od table 8 on page 27 102. rbias a table 9 on page 28 103. gnd - table 9 on page 28 104. tpip1 ai table 6 on page 25 105. tpin1 ai table 6 on page 25 106. vccr - table 9 on page 28 107. tpop1 ao table 6 on page 25 108. tpon1 ao table 6 on page 25 109. gnd - table 9 on page 28 110. tpon2 ao table 6 on page 25 111. tpop2 ao table 6 on page 25 112. vcct - table 9 on page 28 113. vccr - table 9 on page 28 114. tpin2 ai table 6 on page 25 115. tpip2 ai table 6 on page 25 116. gnd - table 9 on page 28 117. gnd - table 9 on page 28 118. tpip3 ai table 6 on page 25 119. tpin3 ai table 6 on page 25 table 2. lxt98x0 pins, numeric order pin symbol type 1,2 reference for full description 1. refer to table 1 for signal type definitions. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 17 120. vccr - table 9 on page 28 121. tpop3 ao table 6 on page 25 122. tpon3 ao table 6 on page 25 123. gnd - table 9 on page 28 124. tpon4 ao table 6 on page 25 125. tpop4 ao table 6 on page 25 126. vcct - table 9 on page 28 127. vccr - table 9 on page 28 128. tpin4 ai table 6 on page 25 129. tpip4 ai table 6 on page 25 130. gnd - table 9 on page 28 131. gnd - table 9 on page 28 132. tpip5 ai table 6 on page 25 133. tpin5 ai table 6 on page 25 134. vccr - table 9 on page 28 135. vcct - table 9 on page 28 136. tpop5 ao table 6 on page 25 137. tpon5 ao table 6 on page 25 138. gnd - table 9 on page 28 139. tpon6 ao table 6 on page 25 140. tpop6 ao table 6 on page 25 141. vccr - table 9 on page 28 142. tpin6 ai table 6 on page 25 143. tpip6 ai table 6 on page 25 144. gnd - table 9 on page 28 145. gnd - table 9 on page 28 146. tpip7 ai table 6 on page 25 147. tpin7 ai table 6 on page 25 148. vccr - table 9 on page 28 149. vcct - table 9 on page 28 150. tpop7 ao table 6 on page 25 151. tpon7 ao table 6 on page 25 152. gnd - table 9 on page 28 153. tpon8 ao table 6 on page 25 table 2. lxt98x0 pins, numeric order pin symbol type 1,2 reference for full description 1. refer to table 1 for signal type definitions. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 18 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 154. tpop8 ao table 6 on page 25 155. vccr - table 9 on page 28 156. tpin8 ai table 6 on page 25 157. tpip8 ai table 6 on page 25 158. gnd - table 9 on page 28 159. txslew_0 i, pd table 6 on page 25 160. txslew_1 i, pd table 6 on page 25 161. port5_led3 o, od table 8 on page 27 162. port5_led2 o, od table 8 on page 27 163. port5_led1 o, od table 8 on page 27 164. gnd - table 9 on page 28 165. port6_led3 o, od table 8 on page 27 166. port6_led2 o, od table 8 on page 27 167. port6_led1 o, od table 8 on page 27 168. gnd - table 9 on page 28 169. port7_led3 o, od table 8 on page 27 170. port7_led2 o, od table 8 on page 27 171. port7_led1 o, od table 8 on page 27 172. gnd - table 9 on page 28 173. vcc - table 9 on page 28 174. port8_led3 o, od table 8 on page 27 175. port8_led2 o, od table 8 on page 27 ledabgsel i 3 , o-od/os table 8 on page 27 176. port8_led1 o, od table 8 on page 27 177. vcc - table 9 on page 28 178. n/c - table 11 on page 30 179. gnd - table 9 on page 28 180. vcc - table 9 on page 28 181. gnd - table 9 on page 28 182. irq o, od table 11 on page 30 183. autoblink/ i 3 , o-od/os table 8 on page 27 act10led i 3 , o-od/os table 8 on page 27 184. ledsel0 i 3 , o-od/os table 8 on page 27 act_100_led i 3 , o-od/os table 8 on page 27 table 2. lxt98x0 pins, numeric order pin symbol type 1,2 reference for full description 1. refer to table 1 for signal type definitions. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 19 185. ledsel1 i 3 , o-od/os table 8 on page 27 col10_led i 3 , o-od/os table 8 on page 27 186. arbselect i 3 , o-od/os table 7 on page 26 col100_led i 3 , o-od/os table 8 on page 27 187. mii2_crs o table 4 on page 21 188. mii2_col o table 4 on page 21 189. gnd - table 9 on page 28 190. vcc - table 9 on page 28 191. mii2_txd3 i table 4 on page 21 192. mii2_txd2 i table 4 on page 21 193. mii2_txd1 i table 4 on page 21 194. mii2_txd0 i table 4 on page 21 195. mii2_txen i table 4 on page 21 196. mii2_txclk o table 4 on page 21 197. mii2_txer i table 4 on page 21 198. arbin i, pd table 7 on page 26 199. gnd - table 9 on page 28 200. vcc - table 9 on page 28 201. mmstrin i, pd table 5 on page 22 202. mii2_rxer o table 4 on page 21 203. mii2_rxclk o table 4 on page 21 204. mii2_rxdv o table 4 on page 21 205. mii2_rxd0 o table 4 on page 21 206. mii2_rxd1 o table 4 on page 21 207. mii2_rxd2 o table 4 on page 21 208. mii2_rxd3 o table 4 on page 21 table 2. lxt98x0 pins, numeric order pin symbol type 1,2 reference for full description 1. refer to table 1 for signal type definitions. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 20 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 3. mii #1 signal descriptions pin symbol type 1, 2 description 9 mii1_spd i pu speed select - mii 1. this signal is sensed at power up, hardware reset, and software reset. selects operating speed of the respective mii (mac) interface. high = 100 mbps. low = 10 mbps. 31 32 34 35 mii1_rxd0 mii1_rxd1 mii1_rxd2 mii1_rxd3 o receive data - mii 1. the lxt98x0 transmits received data to the controller on these outputs. data is driven on the falling edge of mii1_rxclk. 30 mii1_rxdv o receive data valid - mii 1. active high signal, synchronous to mii1_rxclk, indicates valid data on mii1_rxd<3:0>. 29 mii1_rxclk o receive clock - mii 1. mii receive clock for expansion port. this is a 2.5 or 25 mhz clock derived from the clk25 input (refer to table 11 on page 30 ). 26 mii1_rxer o receive error - mii 1. active high signal, synchronous to mii1_rxclk, indicates invalid data on mii1_rxd<3:0>. 24 mii1_txer i transmit error - mii 1. mii1_txer is a 100 mbps-only signal. the mac asserts this input when an error has occurred in the transmit data stream. the lxt98x0 responds by sending ? invalid code symbols ? on the line. 23 mii1_txclk o transmit clock - mii 1. this is a 2.5 or 25 mhz clock derived from the clk25 input (refer to table 11 on page 30 ). 22 mii1_txen i transmit enable - mii 1. external controllers drive this input high to indicate data is transmitted on the mii1_txd<3:0> pins. ground this input if unused. 21 20 19 17 mii1_txd0 mii1_txd1 mii1_txd2 mii1_txd3 i transmit data - mii 1. external controllers use these inputs to transmit data to the lxt98x0. the lxt98x0 samples mii1_txd<3:0> on the rising edge of mii1_txclk, when mii1_txen is high. 14 mii1_col o collision - mii 1. the lxt98x0 drives this signal high to indicate a collision occurred. 13 mii1_crs o carrier sense - mii 1. active high signal indicates lxt98x0 is transmitting or receiving. 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 21 table 4. mii #2 signal descriptions pin symbol type 1, 2 description 18 mii2_spd i pu speed select - mii 2. this signal is sensed at power up, hardware reset, and software reset. selects operating speed of the respective mii (mac) interface. high = 100 mbps. low = 10 mbps. 205 206 207 208 mii2_rxd0 mii2_rxd1 mii2_rxd2 mii2_rxd3 o receive data - mii 2. the lxt98x0 transmits received data to the controller on these outputs. data is driven on the falling edge of mii2_rxclk. 204 mii2_rxdv o receive data valid - mii 2. active high signal, synchronous to mii2_rxclk, indicates valid data on mii2_rxd<3:0>. 203 mii2_rxclk o receive clock - mii 2. mii receive clock for expansion port. this is a 2.5 or 25 mhz clock derived from the clk25 input (refer to table 11 on page 30 ). 202 mii2_rxer o receive error - mii 2. active high signal, synchronous to mii2_rxclk, indicates invalid data on mii2_rxd<3:0>. 197 mii2_txer i transmit error - mii 2. mii2_txer is a 100 mbps-only signal. the mac asserts this input when errors occurs in the transmit data stream. the lxt98x0 sends ? invalid code symbols ? on the line. 196 mii2_txclk o transmit clock - mii 2. this is a 2.5 or 25 mhz clock derived from the clk25 input (refer to table 11 on page 30 ). 195 mii2_txen i transmit enable - mii 2. external controllers drive this input high to indicate data is transmitted on the mii2_txd<3:0> pins. ground this input if unused. 194 193 192 191 mii2_txd0 mii2_txd1 mii2_txd2 mii2_txd3 i transmit data - mii 2. external controllers use these inputs to transmit data to the lxt98x0. the lxt98x0 samples mii2_txd<3:0> on the rising edge of mii2_txclk, when mii2_txen is high. 188 mii2_col o collision - mii 2. the lxt98x0 drives this signal high to indicate a collision occurred. 187 mii2_crs o carrier sense - mii 2. active high signal indicates lxt98x0 is transmitting or receiving. 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 22 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 5. inter-repeater backplane signal descriptions pin symbol type 1, 2 description common irb signals 39 comp_sel ai compatibility mode select. 3.3v on this pin causes the ircfsbp signals to operate in 3.3v only mode. 5v on this pin causes the ir100cfsbp or ir10cfsbp signals to operate in 5v backwards compatibility mode with legacy lxt98x and lxt91x devices. 100 mbps irb signals 36 ir100cfs 3 a i/o od 100 mbps irb collision force sense. a three-level signal that determines number of active ports on the ? logical ? repeater. high level (3.3v) indicates no ports active; mid level (approx. 1.6v) indicates one port active; low level (0v) indicates more than one port active, resulting in a collision. this signal requires a 215 ? pull-up resistor, and connects between ics on the same board. 37 ir100cfsbp a i/o od 100 mbps irb collision force sense - backplane. this three- level signal functions the same as ir100cfs ; however, it connects between ics with chip id = 00, on different boards. ir100cfsbp requires a single 91 ? pull-up resistor in each stack. this signal can be set in either 5v or 3.3v modes by the comp_sel pin. 38 ir100sngl i/o schmitt pu 100 mbps single driver state. this active low signal is asserted by the device with chip id = 00 when a packet is received from one or more ports. do not connect this signal between boards. 40 ir100col i/o schmitt pu 100 mbps multiple driver state. this active low signal is asserted by the device with chip id = 00 when a packet is being received from more than one port (collision). do not connect this signal between boards. 41 ir100den o od 100 mbps irb driver enable. this output provides directional control for an external bidirectional transceiver (74lvt245) used to buffer the 100 mbps irb in multi-board applications. it must be pulled up by a 330 ? resistor. when there are multiple devices on one board, tie all ir100den outputs together. if ir100den is tied directly to the dir pin on a 74lvt245, attach the on-board ir100dat, ir100clk, and ir100dv signals to the ? b ? side of the 74lvt245, and connect the off-board signals to the ? a ? side of the 74lvt245. 42 ir100dv i/o schmitt od pu 100 mbps irb data valid. this active low signal indicates port activity on the repeater. ir100dv frames the clock and data of the packet on the backplane. this signal requires a 300 ? pull-up resistor. 1. i = input, o = output, i/o = input/output, d = digital, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. even if the irb is not used, required pull-up resistors must be installed as listed above. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated. 3. ir100cfs is not 5v tolerant. 4. ir10cfs is not 5v tolerant.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 23 43 44 45 48 49 ir100dat0 ir100dat1 ir100dat2 ir100dat3 ir100dat4 i/o tri-state schmitt pu 100 mbps irb data. these bidirectional signals carry 5-bit data on the 100 mbps irb. data is driven on the falling edge and sampled on the rising edge of ir100clk. buffer these signals between boards. 50 ir100clk i/o tri-state schmitt pd 100 mbps irb clock. this bidirectional, non-continuous, 25 mhz clock is recovered from received network traffic. schmitt triggering is used to increase noise immunity. this signal must be pulled to vcc when idle. one 1 k ? pull-up resistor on both sides of a 74lvt245 buffer is recommended. 56 ir100iso o 100 mbps stack backplane isolate. this output allows one lxt98x0 per board the ability to enable or disable an external bidirectional transceiver (74lvt245). attach the output to the enable input of the 74lvt245. the output is driven high (disable) to isolate the 100 mbps irb. 10 mbps irb signals 11 ir10dat i/o od pd 10 mbps irb data. this bidirectional signal carries data on the 10 mbps irb. data is driven and sampled on the rising edge of the corresponding irclk. this signal must be pulled high by a 330 ? resistor. buffer this signal between boards. 12 ir10clk i/o tri-state schmitt pd 10 mbps10 mbps irb clock. this bidirectional, non-continuous, 10 mhz clock is recovered from received network traffic. during idle periods, the output is high-impedance. schmitt triggering is used to increase noise immunity. 6 ir10den o od 10 mbps irb driver enable. this output provides directional control for an external bidirectional transceiver (74lvt245) used to buffer the irbs in multi-board applications. it must be pulled up by a 330 ? resistor. when there are multiple devices on one board, tie all ir10den outputs together. if ir10den is tied directly to the dir pin on a 74lvt245, attach the on-board ir10dat, ir10clk and ir10ena signals to the ? b ? side of the 74lvt245, and connect the off-board signals to the ? a ? side of the 74lvt245. 10 ir10ena i/o od pu 10 mbps irb enable. this active low output indicates carrier presence on the irb. a 330 ? pull-up resistor is required to pull the ir10ena output high when the irb is idle. when there are multiple devices, tie all ir10ena outputs together. buffer these signals between boards. 3 ir10col i/o od pu 10 mbps irb collision. this output is driven low to indicate a collision occurred on the 10 mbps segment. a 330 ? resistor is required on each board to pull this signal high when there is no collision. do not connect between boards and do not buffer. table 5. inter-repeater backplane signal descriptions (continued) pin symbol type 1, 2 description 1. i = input, o = output, i/o = input/output, d = digital, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. even if the irb is not used, required pull-up resistors must be installed as listed above. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated. 3. ir100cfs is not 5v tolerant. 4. ir10cfs is not 5v tolerant.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 24 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 4 ir10colbp i/o od 10 mbps irb collision - backplane. this active low output has the same function as ir10col , but is used between boards. attach this signal only from the device with chip id = 00 to the backplane or connector, without buffering . the output must be pulled up by one 330 ? resistor per stack. 2 ir10cfs 4 a, i/o od 10 mbps irb collision force sense. this three-state analog signal indicates transmit collision when driven low. ir10cfs requires a 215 ? , 1% pull-up resistor. do not connect this signal between boards and do not buffer. 5 ir10cfsbp a i/o od 10 mbps irb collision force sense - backplane. functions the same as ir10cfs , but connects between boards. attach this signal only from the device with chip id = 0 to the backplane or connector, without buffering . this signal requires one 330 ? , 1% pull-up resistor per stack. this signal can be set for 5v or 3.3v modes by the comp_sel pin. 80 macactive i pd mac active. active high input allows external asics to participate in 10 mbps irb. driving data onto the irb requires the external asic assert macactive high for one clock cycle, then assert ir10ena low. asic monitors ir10col (active low) for collision. by using macactive, the repeater ? not the mac ? drives the three-level ir10cfs pin. 55 ir10iso o 10 mbps irb isolate. by using ir10 iso, one lxt98x0 per board can enable or disable an external bidirectional transceiver (74lvt245). attach the output to the enable input of the 74lvt245. driven high (disable) to isolate the 10 mbps irb. 81 holdcol i/o pd hold collision for 10 mbps mode. this active high signal is driven by the device with chip id = 00 to extend a non-local transmit collision to other devices on the same board. do not attach the holdcol signals from different boards together. 201 mmstrin i pd management master input. the management master (mm) daisy chain ensures collisions are counted correctly in multi-board applications. attach the mmstrin input of each device to the mmstrout output of the previous device. ground mmstrin of the first or only device. 64 mmstrout o management master output. mm daisy chain output. in hot- swap applications, a 1 k ? - 3 k ? resistor can be used as a by- pass between mmstrin and mmstrout. table 5. inter-repeater backplane signal descriptions (continued) pin symbol type 1, 2 description 1. i = input, o = output, i/o = input/output, d = digital, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. even if the irb is not used, required pull-up resistors must be installed as listed above. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated. 3. ir100cfs is not 5v tolerant. 4. ir10cfs is not 5v tolerant.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 25 table 6. twisted-pair port signal descriptions pin symbol type 1 description 107, 108 111, 110 121, 122 125, 124 136, 137 140, 139 150, 151 154, 153 tpop1, tpon1 tpop2, tpon2 tpop3, tpon3 tpop4, tpon4 tpop5, tpon5 tpop6, tpon6 tpop7, tpon7 tpop8, tpon8 ao twisted-pair outputs - ports 1 through 8. these pins are the positive and negative outputs from the respective ports ? twisted-pair line drivers. for unused ports, these pins can be left open. 104, 105 115, 114 118, 119 129, 128 132, 133 143, 142 146, 147 157, 156 tpip1, tpin1 tpip2, tpin2 tpip3, tpin3 tpip4, tpin4 tpip5, tpin5 tpip6, tpin6 tpip7, tpin7 tpip8, tpin8 ai twisted-pair inputs - ports 1 through 8. these pins are the positive and negative inputs to the respective ports ? twisted- pair receivers. for unused ports, tie together with 100 ? resistors and float. 160 159 txslew_1 txslew_0 i pd tx output slew controls 0 and 1 . these pins select the tx output slew rate (rise and fall time) as follows: txslew_1 txslew_0 slew rate (rise and fall time) 0 0 2.5 ns 0 1 3.1 ns 1 0 3.7 ns 1 1 4.3 ns 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, ao = analog output, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 26 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 7. serial management interface signal descriptions pin symbol type 1, 2, description 57 reconfig i pd reconfigure . this input determines whether serclk is an input or an output. when reconfig is high, the lxt98x0 drives serclk with a 625 khz output. when reconfig is low, serclk is an input to the lxt98x0. if the lxt98x0 detects a low-to-high transition on reconfig, or if reconfig is high at power-up, it sends out a ? configuration change ? message (start flag with all 0s) on the bus. 63 ser_match o serial match. the lxt98x0 device with chip id = 00 asserts this active high output whenever it detects a message on the smi matching the local hub id. see ? serial management i/f ? on page 52. 58 srx i pd serial receive. receive data input for smi. must be tied to stx externally. srx is sampled on the rising edge of serclk. 59 stx o od serial transmit. transmit data output for smi. must be tied to srx externally. data transmitted on stx is compared with data received on srx. in the event of a mismatch, stx goes to a high impedance state. stx is driven on the falling edge of serclk. 60 serclk i/o tri-state pd serial clock. clock for smi. depending on reconfig, this pin is either a 625 khz output or a 0 to 2 mhz input. 198 arbin i pd arbitration in/out . used with chain arbitration. if used, tie arbin to arbout of the previous device. arbin at the top of the daisy chain can be connected to ground or to arbout of the scc. if unused, tie arbin high. 65 arbout o 186 arbselect i 3 o - od/os arbitration mode select - input. 0 = prom based, 1 = chain based. this configuration pin also functions as the col100 led output (refer to note 3 below and to table 8 ). 67 mgr_pres i pu manager present. this signal is sensed at power up, hardware reset, and software reset. if the signal is high, it indicates no local manager is present, and the lxt98x0 enables all ports and sets all leds to operate in ? hardware mode ? . if it is low, indicating a manager is present, the lxt98x0 disables all ports, pending control of network manager. 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated. 3. input must be static. refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 27 table 8. led signal descriptions pin symbol type 1, 2 description 184 185 ledsel0 ledsel1 i 3 o - od/os led mode select - input. see note 3 in footer below. 00 = mode 1, 01 = mode 2, 10 = mode 3, 11 = mode 4 these pins are shared with the ledact100, ledcol10 outputs. 175 ledabgsel i 3 o - od/os led activity bar graph mode select - input. see note 2 in footer below. 0 = base-10 mode, 1 = base-2 mode refer to ? activity graph leds ? on page 59. this pin is shared with the port8_led2 output. 183 autoblink i 3 o - od/os led blink mode select - input. see note 3 in footer below. 0 = auto blink on, 1 = auto blink off this pin is shared with the ledact10 output. 83 leddat o led data . serial data stream that is shifted into external serial- to-parallel led drivers. see ? serial led interface ? on page 40 . 84 ledlat o led latch . parallel load clock for external serial-to-parallel led drivers. see ? serial led interface ? on page 40 . 82 ledclk cfg_clk o led clock . serial data stream clock for external serial-to- parallel led drivers. see ? serial led interface ? on page 40 . configuration bus clock. refer to cfg_dt and cfg_ld pin description in table 11 on page 30 . cfg_clk pulses whenever a read of the serial configuration register occurs. see ? serial configuration interface ? on page 60. 176 171 167 163 101 97 93 89 port8_led1 port7_led1 port6_led1 port5_led1 port4_led1 port3_led1 port2_led1 port1_led1 o od led driver 1 - ports 1 through 8 . programmable led driver. active low. see ? direct drive leds ? on page 42. port8_led1 must be pulled high via a 100 ? 500k ? resistor if led circuit not used. 175 170 166 162 100 96 92 88 port8_led2 port7_led2 port6_led2 port5_led2 port4_led2 port3_led2 port2_led2 port1_led2 o od led driver 2 - ports 1 through 8 . programmable led driver. active low. see ? direct drive leds ? on page 42. the port8_led2 pin is shared with the ledabgsel configuration input. 174 169 165 161 99 95 91 87 port8_led3 port7_led3 port6_led3 port5_led3 port4_led3 port3_led3 port2_led3 port1_led3 o od led driver 3 - ports 1 through 8 . programmable led driver. active low. see ? direct drive leds ? on page 42. port8_led3 must be pulled high via a 100 ? 500 k ? resistor if led circuit not used. 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. even if the irb is not used, required pull-up resistors must be installed as listed above. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 28 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 185 col10_led i o - od/os 10 mbps collision led driver . active output indicates collision on 10 mbps segment. this pin is shared with the ledsel1 configuration input. 186 col100_led i o - od/os 100 mbps collision led driver . active output indicates collision on 100 mbps segment. this pin is shared with the arbselect configuration input (refer to table 7 on page 26 and to note 3 below). 183 act10_led i o - od/os 10 mbps activity led driver . active output indicates activity on 10 mbps segment. this pin is shared with the autoblink configuration input (refer to note 3 below). 184 act100_led i o - od/os 100 mbps activity led driver . active output indicates activity on 100 mbps segment. this pin is shared with the ledsel0 configuration input (refer to note 3 below). table 9. power supply and indication signal descriptions pin symbol type 1, 2 description 8, 16, 28, 47, 61, 74, 76, 77, 85, 173, 177, 180, 190, 200 vcc - power supply inputs. each of these pins must be connected to a common +3.3 vdc power supply. a de-coupling capacitor to digital ground should be supplied for every one of these pins. 106, 113, 120, 127, 134, 141, 148, 155 vccr - analog supply inputs - receive. each of these pins must be connected to a common +3.3 vdc power supply. a de-coupling capacitor to gnd should be supplied for every one of these pins. use ferrite beads to create a separate analog vcc plane. 112, 126, 135, 149 vcct - analog supply inputs - transmit. each of these pins must be connected to a common +3.3 vdc power supply. a de-coupling capacitor to gnd should be supplied for every one of these pins. use ferrite beads to create a separate analog vcc plane. 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated. table 8. led signal descriptions (continued) pin symbol type 1, 2 description 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. even if the irb is not used, required pull-up resistors must be installed as listed above. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated. 3. input must be static; refer to ? led pins multiplexed with configuration inputs ? on page 69 for information on pin use.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 29 1, 7, 15, 27, 46, 62, 75, 86, 90, 94, 98, 103, 109, 116, 117, 123, 130, 131, 138, 144, 145, 152, 158, 164, 168, 172, 179, 181, 189, 199 gnd - ground. connect each of these pins to system ground plane. 102 rbias a rbias. used to provide bias current for internal circuitry. the 100 a bias current is provided through an external 22.1 k ?, 1% resistor to gnd. 79 rps_pres i pd redundant power supply present. active high input indicates presence of redundant power supply. tie low if not used. 78 rps_fault i pu redundant power supply fault. active low input indicates redundant power supply fault. the state of this input is reflected in the rps_led output (refer to led section). tie high if not used. table 9. power supply and indication signal descriptions (continued) pin symbol type 1, 2 description 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated. table 10. prom interface signal descriptions pin symbol type 1, 2 description 68 prom_clk i/o tri-state pd prom clock. 1 mhz clock for reading prom data (chip id = 00). if a prom is not used, this pin must be tied low. all devices should be connected together. prom_clk is driven only by the device with chipid = 00. (sensed by other devices.) 69 prom_cs o tri-state prom chip select. selects prom. active high signal driven only when chip id = 00. 70 prom_dtout o tri-state prom data output. selects read instruction for prom. active high signal driven only when chipid = 00. all devices should be connected together. prom_clk is driven only by the device with chipid = 00. (sensed by other devices.) 71 prom_dtin i pd prom data input. if a prom is not used, this input can be tied low or high. 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 30 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 11. miscellaneous signal descriptions pin symbol type 1, 2 description 53 reset i schmitt reset. this active low input causes internal circuits, state machines and counters to reset (address tracking registers do not reset). on power-up, devices should not be brought out of reset until the power supply stabilizes to 3.3v. when there are multiple devices, it is recommended all be supplied by a common reset driven by an ? ls14 or similar device. 54 clk25 i schmitt 25 mhz system clock. refer to table 29 on page 75 for clock requirements. 72 73 chipid0 chipid1 i pd chip id. these pins assign unique chip ids to as many as four devices on a single board. one device on each board must be assigned chipid = 00. see ? serial management i/f ? on page 52 . 33 config(0) / cfg_dt i pd configuration register input 0. the config[1:0] inputs allow the user to store system-specific information (board type, plug-in cards, status, etc.) in the serial configuration register (hex address ac). this register may be read remotely through the serial management interface (smi). configuration bus data. used in conjunction with cfg_clk and cfg_ld , these pins provide an expansion capability for the functionality of config[1:0]. using an external parallel-to-serial device, up to 8 configuration inputs can be brought to the smi for user access. the configuration mode select bit (bit 14) in the repeater configuration register is used to choose between config[1:0] and cfg bus modes. (see table 75 on page 109 .) 25 config(1) / cfg_ld i/o pd configuration register input 1. the config[1:0] inputs allow the user to store system-specific information (board type, plug-in cards, status, etc.) in the repeater serial configuration register. this register may be read remotely through the serial management interface (smi). configuration bus load (active low) . used in conjunction with cfg_clk and cfg_dt, this active low pin provides an expansion capability for the functionality of config[1:0]. using an external parallel-to-serial device, up to 8 config. inputs can be brought to the smi for user access. the configuration mode select bit (bit 14) in the repeater configuration register is used to choose between config[1:0] and cfg bus modes. see table 75 on page 109 .) 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 31 3.0 functional description 3.1 introduction as a fully integrated ieee 802.3 compliant repeater capable of 10 mbps and 100 mbps operation, the lxt98x0 is a versatile device allowing great flexibility in ethernet design solutions. figure 3 shows a typical application. refer to ? application information ? on page 61 for specific circuit implementations. this multi-port repeater provides six (lxt9860) or eight (lxt9880) 10base-t/100base-tx ports. in addition, each device also provides two media independent interface (mii) expansion ports that may be connected to 10/100 macs. the lxt98x0 provides two repeater state machines and two inter-repeater backplanes (irb) on a single chip ? one for 10 mbps and one for 100 mbps operation. the 100 mbps repeater meets ieee 802.3 class ii requirements. each port ? s operating speed may be selected independently. the auto- negotiation capability of the lxt98x0 allows it to communicate with connected nodes and configure itself accordingly. the lxt98x0 supports rmon by providing on-chip counters and hardware assistance for a fully managed environment. the segmented backplane simplifies dual-speed operation, and allows multiple devices to be stacked and function as one logical class ii repeater. up to 240 ports (192 tp ports and 48 mii ports) can be supported in a single stack. 82 cfg_clk/ ledclk o configuration bus clock. refer to cfg_dt and cfg_ld pin description. cfg_clk pulses whenever a read of the serial configuration register occurs. refer to ? serial configuration interface ? on page 60 . led clock . serial data stream clock for external serial-to- parallel led drivers. refer to table 8 for details. 182 irq o od interrupt request. active low interrupt. refer to register section for criteria and clearing options. requires an external pull-up resistor. 51, 52, 66,178 nc - no connects. leave these pins unconnected. table 11. miscellaneous signal descriptions (continued) pin symbol type 1, 2 description 1. i = input, o = output, i/o = input/output, d = digital, a = analog, ai = analog input, a i/o = analog input/output, od = open drain, os = open source, pd = pull down, pu = pull up. nc = no clamp. pad does not clamp input in the absence of power. 2. pins are 5v tolerant, unless indicated.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 32 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.2 port configuration the lxt98x0 powers up in auto-negotiation mode for all twisted-pair ports. software can monitor or change the configuration through the phy port control register. 3.2.1 auto-negotiation all tp ports on power up are configured to establish its link via auto-negotiation. the port and its link partner establish link conditions by exchanging fast link pulse (flp) bursts. each flp burst contains 16 bits of data advertising the port ? s capabilities. the flp bursts sent by the port are maintained in its auto-negotiation advertisement register ( table 71 on page 107 ). the link partner ? s abilities are stored in the auto-negotiation link partner register ( table 66 on page 104 ). status can be observed in the respective auto-negotiation status register ( table 65 on page 104 ). each port has its own advertisement, link partner advertisement, auto-negotiation expansion, auto-negotiation status registers, and control register. the advertisement register is read-only, except for bits 5, 7, and 13. the lxt98x0 can advertise 100 mbps half-duplex and/or 10 mbps half-duplex; it never advertises full duplex. if the link partner does not support auto-negotiation, the lxt98x0 determines link state by listening for 100 mbps idle symbols or 10 mbps link pulses. if it detects either of these signals, it configures the port and updates the status registers appropriately. figure 3. typical lxt988x managed repeater architectures lxt9880 ic device management 10base-t repeater 100base- x repeater led drivers rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port 10/100 phy 10/100 phy mii mii 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy lxt9880 ic device management 10base-t repeater 100base- x repeater led drivers rmon & snmp counters 10 mbps backplane 100 mbps backplane serial port 10/100 phy 10/100 phy mii mii 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy lxt9880 ic device management 10base-t repeater 100base-x repeater led drivers rmon & snmp counters 10mbps backplane 100mbps backplane serial port 10/100 phy 10/100 phy mii mii 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy 10/100 phy serial management to scc buffer 100m backplane 100m backplane buffer 10m backplane mii to mii bridge 10m backplane
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 33 3.2.2 forced operation a port can be directly configured to operate in either 100base-tx or 10base-t. when a port is configured for forced operation, it immediately operates in the selected mode. all links are established as half-duplex only. as a repeater, the lxt98x0 cannot support full-duplex operation. 3.2.3 changing port speed - forced to force a port speed change while operating, the following sequence is required: disable the port(s) to be changed. set phy port control register to desired speed. perform a repeater reset (at register 144; see table 83 on page 113 . the lxt98x0 does not read hardware configuration pins). re-enable the port(s). note: forcing a speed change on any port requires a repeater reset. 3.2.4 link establishment and port connection once a port establishes link, the lxt98x0 automatically connects it to the appropriate repeater state machine. if link loss is detected, the port returns to the auto-negotiation state. 3.2.5 mii port configuration these ports can be set via hardware tie ups/downs to be either 10 mbps or 100 mbps. the statistics for these ports are the same as for the other 10/100 ports, except isolation, partition, and symbol error. 3.3 interface descriptions the lxt9880 and lxt9860 devices provide eight and six network interface ports, respectively. each port provides a twisted-pair interface. the twisted-pair interface directly supports 100base- tx and 10base-t. ethernet applications and fully complies with ieee 802.3 standards. a common termination circuit is used. 3.3.1 twisted-pair interface the lxt98x0 pinout is optimized for dual-height rj-45 connectors. the twisted-pair interface for each port consists of two differential signal pairs ? one for transmit and one for receive. the transmit signal pair is tpop/tpon, the receive signal pair is tpip/tpin. the transmitter requires magnetics with 1:1 turns ratio. the center tap of the primary side of the transmit winding must be tied to a quiet vcc for proper operation. when the twisted-pair interface is disabled, the transmitter outputs are tri-stated. the receiver requires magnetics with a 1:1 turns ratio, and a load of 100 ? . when the twisted-pair port is enabled, the receiver actively biases its inputs to approximately 2.8v. when the twisted-pair interface is disabled, no biasing is provided. a 4 k ? load is always present across the tpip/tpin pair.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 34 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 when used in 100base-tx applications, the lxt98x0 sends and receives a continuous, scrambled 125mbaud mlt-3 waveform on this interface. in the absence of data, idle symbols are sent and received in order to maintain the link. when used in 10base-t applications, the lxt98x0 sends and receives a non-continuous, 10 mbaud manchester-encoded waveform. to maintain link during idle periods, the lxt98x0 sends link pulses every 16 ms, and expects to receive them every 10 to 20ms. each 10base-t port automatically detects and sends link pulses, and disables its transmitter if link pulses are not detected. each receiver can also be configured to ignore link pulses, and leave its transmitter enabled all the time (link pulse transmission cannot be disabled). each 10base-t port can detect and automatically correct for polarity reversal on the tpip/n inputs. the 10base-t interface provides integrated filters using intel ? s patented filter technology. these filters facilitate low-cost stack designs to meet emi requirements. 3.3.2 media independent interface the lxt98x0 has two identical mii interfaces. the mii has been designed to allow expansion to a media access controller (mac) as shown in figure 4 . this interface is not mdio/mdc capable. management is provided via a serial controller interface. these mii ports can be set via hardware tie ups/downs to be either 10 mbps or 100 mbps100 mbps. the statistics kept for these ports are the same as for the other 10/100 ports, except isolation, partition, and symbol error. these ports are not the full mii drive strength and are intended only for point-to-point links. serial terminations are recommended. 3.3.3 serial management interface the serial management interface (smi) provides system access to the status, control and statistic gathering abilities of the lxt98x0. this interface allows multiple devices to be managed from a common line, and uses the minimum number of signals (2) for ease of stack design. the interface itself consists of two digital nrz signals ? clock and data. refer to table 7 on page 26 for smi pin assignments and signal descriptions. data is framed into hdlc-like packets, with a start/stop flag, header and crc field for error checking. zero-bit insertion/removal is used. the interface can operate at any speed from 0 to 2 mhz. ( ? 0 mhz ? means the clock need not be continuous. it can be started, stopped, or restarted, provided sixteen 1s in a row are allowed between management packets.) figure 4. mii interface mac txd(3:0) txen txer txclk rxclk lxt98x0 rxd(3:0) rx_dv rx_er crs col
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 35 address assignment is provided via one of two arbitration mechanisms which are activated whenever the device is powered up or reset/reconfigured. refer to ? serial management i/f ? on page 52 . 3.3.4 serial prom interface the serial prom interface allows the loading of optional information unique to each board. items such as serial number or date of manufacture can be placed in the serial prom, which is also used in the address arbitration process. see ? serial prom interface ? on page 59 . 3.4 repeater operation the lxt98x0 contains two internal repeater state machines ? one operating at 10 mbps and the other at 100 mbps. the lxt98x0 automatically switches each port to the correct repeater, once the operational state of that port has been determined. each repeater connects all ports configured to the same speed (including the mii), and the corresponding inter-repeater backplane. both repeaters perform the standard jabber and partition functions. 3.4.1 100 mbps repeater operation the lxt98x0 contains a complete 100 mbps repeater state machine (100rsm) that is fully ieee 802.3 class ii compliant. any port configured for 100 mbps operation is automatically connected to the 100 mbps repeater. this includes any of the eight media and two mii ports configured for 100 mbps operation. the 100 mbps rsm has its own inter-repeater backplane (100irb). multiple lxt98x0s can be cascaded on the 100irb and operate as one repeater segment. data from any port is forwarded to all other ports in the cascade. the 100irb is a 5-bit symbol-mode interface. it is designed to be stackable. the lxt98x0 maintains a complete set of statistics for its local 100 mbps repeater segment. these are accessible through the high-speed serial management interface. the lxt98x0 performs the following 100 mbps repeater functions: signal amplification, wave-shape restoration, and data-frame forwarding. sop, soj, eop, eoj delay < 46bt; class ii compliant. collision enforcement. during a 100 mbps collision, the lxt98x0 drives a 0101 jam signal (encoded as data 5 on tx links) to all ports until the collision ends. there is no minimum enforcement time. partition. the lxt98x0 partitions any port that participates in excess of 60 consecutive collisions or one long collision approximately 575.2 s long. once partitioned, the lxt98x0 monitors and transmits to the port, but does not repeat data received from the port until it un- partitions. un-partition. the lxt98x0 supports two un-partition algorithms: ? the alternative un-partition algorithm (default), which complies with ieee specification 802.3aa un-partitions a port on either transmit or receive of at least 450-560 bits without collision.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 36 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 ? the normal algorithm, which complies with the ieee specification 802.3u, is available through the management interface. this algorithm un-partitions a port only when data is transmitted to the port for 450-560 bit times without a collision. isolate. the lxt98x0 isolates any port receiving more than two successive false carrier events. a false carrier event is a packet that does not start with a /j/k symbol pair. note: this is not the same function as the 100irb isolate function, which involves isolating the backplane. un-isolate. the lxt98x0 un-isolates a port that remains in the idle state for 33000 +/- 25% bt or that receives a valid frame at least 450-500 bt in length. /t/r generation. the lxt98x0 can insert a /t/r symbol pair (end-of-stream delimiter) on any incoming packet that does not include one. this feature is optional, and is enabled through the management interface. jabber. the lxt98x0 ignores any receiver remaining active for more than 57,500 bit times. the lxt98x0 exits this state when either one of the following conditions is met: ? on power-up reset ? when carrier is no longer detected note: the isolate, partition, and symbol error functions do not apply to mii ports. 3.4.2 10 mbps repeater operation the lxt98x0 contains a complete 10 mbps repeater state machine (10rsm) that is fully ieee 802.3 compliant. any port configured for 10 mbps operation is automatically connected to the 10 mbps repeater. this includes any of the media and mii ports configured for 10 mbps operation. the 10rsm has its own inter-repeater backplane (10irb). multiple lxt98x0s can be cascaded on the 10irb and operate as one repeater segment. data from any port is forwarded to all other ports in the cascade. the lxt98x0 maintains a complete set of statistics on its 10 mbps repeater segment. these are accessible through the high-speed serial management interface. the lxt98x0 performs the following 10 mbps repeater functions: signal amplification, wave-shape restoration, and data-frame forwarding. preamble regeneration. all outgoing packets have a minimum 56-bit preamble and 8-bit sfd. sop, soj, eop, eoj delays meet ieee 802.3 section 9.5.5 and 9.5.6 requirements. collision enforcement. during a 10 mbps collision, the lxt98x0 drives a jam signal ( ? 1010 ? ) to all ports for a minimum of 96 bit times until the collision ends. partition. the lxt98x0 partitions any port in excess of 31 consecutive collisions. once partitioned, the lxt98x0 continues monitoring and transmitting to the port, but does not repeat data received from the port until it properly un-partitions. (also partitions for excessive length of a collision.) un-partition. the algorithm, which complies with the ieee 802.3 specification, un-partitions a port when data can be either received or transmitted from the port for 450-560 bit times without a collision on that port. jabber. the lxt98x0 asserts a minimum-ifg idle period when a port transmits for longer than 40,000 to 75,000 bit times.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 37 3.5 management support 3.5.1 configuration and status the lxt98x0 provides management control and visibility of the following functions: counter reset and zeroing auto-negotiation (control, status, advertisement, link partner, and expansion) device and board configuration led functions source address tracking (per port) source address matching (per chip) device/revision id 3.5.2 snmp and rmon support the lxt98x0 provides snmp and rmon support through its statistics gathering function. statistics are gathered on all packets flowing through the device for each of the ports, including the mii. the lxt98x0 maintains statistics for both the entire 10 mbps and 100 mbps repeaters, independent of the speed setting of the mii ports. all statistics are stored in 32- or 64-bit registers. per-port counters include: 3.5.3 source address management the lxt98x0 provides two source address management functions per port: source address tracking and source address matching. these functions allow a network manager to track source addresses at each port, or to identify any port sourcing a particular address. 3.6 requirements 3.6.1 power the lxt98x0 has four types of +3.3v power supply input pins: two digital (vcc, gnd) and two analog (vccr, vcct). these inputs may be supplied from a single source. ferrite beads should be used to separate the analog and digital planes. these supplies should be as clean as possible. each supply input should be decoupled to ground. refer to table 9 on page 28 for power and ground pin assignments, and to the ? general design guidelines ? on page 61 . readable frames readable octets fcs errors alignment errors framestoolong shortevents runts collisions lateevents verylongevents dataratemismatch autopartitions broadcast multicast sa changes isolates symbol errors
lxt9860/9880 ? advanced 10/100 repeater with integrated management 38 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.6.2 clock a stable, external 25 mhz reference clock source (ttl) is required to the clk25 pin. the reference clock is used to generate transmit signals and recover receive signals. a crystal-based clock is recommended over a derived clock (i.e., pll-based) to minimize transmit jitter. refer to table 26 on page 67 for a list of recommended oscillators and to table 29 on page 75 for clock timing requirements. 3.6.3 bias resistor the rbias input requires a 22.1 k ? , 1% resistor connected to ground. 3.6.4 reset at power-up, the reset input must be held low until vcc reaches at least 3.15v. a buffer should be used to drive reset if there are multiple lxt98x0 devices. the clock must be active. software and hardware resets are identical. refer to table 74 on page 108 and table 84 on page 113 for software reset details. 3.6.5 prom although not required, an external, auto-incrementing 48-bit prom can be used for two purposes: support the prom-based address arbitration scheme on the serial management interface (see ? prom arbitration mechanism ? on page 58 .) assign a unique id and upload configuration data to all lxt98x0s on a board multiple devices on the same board can share a single common prom. the lxt98x0 with chipid = 00 actively reads the prom at power-up; all other lxt98x0s ? listen in ? . if prom arbitration is not used, the prom data input signal must be tied either high or low. (see ? serial prom interface ? on page 59 .) 3.6.6 chip id each cascaded lxt98x0 requires a unique 2-bit chip id value. the serial management interface (smi) identifies each ic by chipid. one lxt98x0 on each board must be assigned chipid = 00. in the header field, the chip address is defined by three bits. the most significant bit (msb) = 0; the value of the other two bits is set by pins. refer to ? serial management i/f ? on page 52 . 3.6.7 management master i/o link in multiple device applications, the management master daisy chain (mmstrin/mmstrout) ensures that collisions are counted correctly. connect the mmstrin input to the mmstrout output of the previous device when cascading and stacking. ground the mmstrin input of the first or only device. in hot-swap applications, resistive bypassing can be used with a 1 - 3 k ? value. 3.6.8 irb bus pull-ups even when the lxt98x0 is used in a stand-alone configuration, pull-up resistors are required on the irb signals listed. see figure 30 on page 74 and figure 31 on page 74 for sample circuits.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 39 3.7 led operation the lxt98x0 drives the most commonly used leds directly (see ? direct drive leds ? on page 42 ). the less frequently used leds are optionally driven via a serial bus to inexpensive serial-to-parallel devices (see ? serial leds ? on this page). 3.7.1 leds at start-up for approximately 2 seconds after the lxt98x0 is reset, all leds are driven to the on state. this start-up routine is an led check. 3.7.2 led event stretching short lived led status events are stretched so they may be observed by the human eye. refer to the led1, 2, 3 modes section for stretching specifics. 3.7.3 led blink rates two programmable blink rates are provided. the default period for the slow blink rate is 1.6s. the default period is 0.4s for the fast blink rate. these rates may be changed via the led timer control register. the slow blink rate is defined by the upper 8 bits and the fast blink rate is defined by the lower 8 bits of the led timer control register. refer to ? led timer control register ? on page 112 for details. 100 mbps irb 10 mbps irb ir100cfs ir10dat ir100cfsbp ir10ena ir100dv ir10col ir100clk ir10cfs ir10colbp ir10cfsbp figure 5. led blink rates time on solid slow blink fast blink off
lxt9860/9880 ? advanced 10/100 repeater with integrated management 40 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.7.4 serial led interface the lxt98x0 provides a serial interface to drive additional leds via external 8-bit serial-to- parallel converters. a maximum of 30 leds can be driven, using four s/p devices. collision10/ 100, activity10/100 status indications are output on multiplexed configuration pins and are duplicated on the serial port. (see ? led pins multiplexed with configuration inputs ? on page 69 .) 3.7.4.1 serial shifting figure 6 shows the serial led shift loading. 3.7.4.2 serial led signals the led serial interface bus consists of three lxt98x0 outputs: clock (ledclk), parallel load clock (ledlat), and output data (leddat). refer to table 8 on page 27 for signal descriptions and to figure 28 on page 71 for an illustration of the led serial interface circuit. refer to figure 7 and table 12 for details on the led serial bit stream. figure 6. serial led shift loading 74x164 74x164 74x164 74x164 2 lxt98xx mii misc act10 act100 3 14 8 57 6 mii 1, 2, 3 misc activity 10 mbps activity 100 mbps shift order mii1 led1 collision 10 mbps actg8 actg8 8 mii1 led2 collision 100 mbps actg7 actg7 7 mii1 led3 manager present actg6 actg6 6 mii2 led1 activity 10 mbps actg5 actg5 5 mii2 led2 activity 100 mbps actg4 actg4 4 mi2 led3 global fault actg3 actg3 3 not used not used actg2 actg2 2 not used rps fault actg1 actg1 1 30 leds
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 41 3.7.4.3 activity graph leds the actgled10 and actgled100 leds are for activity bar graphing. the activity information is integrated and updated over a period of 328.125 ms, which has the effect of smoothing out the activity. leds are provided for both the 10 mbps and 100 mbps segments. there are two display modes for the activity bar graphs, base-2 and base-10. the modes are selected via the ledabgsel pin. refer to table 13 for details. each step led on the bar graph is lit when the percent activity value associated with that step is met or exceeded. figure 7. serial led port signaling table 12. serial led port bit stream bit mii ports-led1, 2, 3 misc. actgled10 actgled100 7 mii port 1 - led1 collision - 10m 1 actg8 actg8 6 mii port 1 - led2 collision - 100m 1 actg7 actg7 5 mii port 1 - led3 manager present actg6 actg6 4 mii port 2 - led1 activity - 10m 1 actg5 actg5 3 mii port 2 - led2 activity - 100m 1 actg4 actg4 2 mii port 2 - led3 global fault actg3 actg3 1 not used not used actg2 actg2 0 not used rps fault actg1 actg1 1. these leds are multiplexed with configuration inputs. leddat mii ports-led1,2,3 misc. leds actgled10 actgled100 time ledlat leddat ledlat b0 b1 b2 b3 b4 b5 b6 b7 ledclk qa ? -qh ? ( ? 595) qa-qh ( ? 164) b0, b7-b1 b1, b0, b7-b2 b2-b0, b7-b3 b3-b0, b7-b4 b4-b0, b7-b5 b5-b0, b7-b6 b6-b0, b7 b7-b0 b7-b0 qa-qh ( ? 595) b7-b0 b7-b0 leddat ledlat ledclk 122 s 100 ns / 10 mhz
lxt9860/9880 ? advanced 10/100 repeater with integrated management 42 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.7.5 direct drive leds the lxt98x0 provides three direct drive leds for each port (port n _led1:3), excluding the two mii ports. four additional segment leds indicate collision 10/100 and activity 10/100. the per- port leds are updated simultaneously to illustrate clear, non-overlapping status. the following device pins are multifunctional (input = configuration; output = led driver): col10_led (185), col100_led (186), act10_led (183), act100_led (184), and, port8_led2 (175) . the led drive level is determined by the particular input configuration function of the respective pin. collision and activity indications for both 10 mbps and 100 mbps segments are available in both serial and direct drive. direct drive led outputs can be overridden by software control. two bits per port configure the leds to one of four states: led off led on led fast blink led under hardware control 3.7.6 led modes the four available led modes are described in table 15 - table 18 . hardware pins provide global led mode control. refer to table 8 on page 27 for pin assignments and signal descriptions. software can configure each port individually to operate in any mode. refer to ? port led control register ? on page 111 . ? led global control register ? on page 111 outlines how the global leds are similarly controlled. table 14 defines terms used to describe led operation. table 13. actgled display modes led ledabgsel = 0 (base-10) ledabgsel = 1 (base-2) actg 8 60+% activity 80+% activity actg 7 50% activity 64% activity actg 6 40% activity 32% activity actg 5 30% activity 16% activity actg 4 20% activity 8% activity actg 3 10% activity 4% activity actg 2 5% activity 2% activity actg 1 1% activity 1% activity
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 43 table 14. led terms term definition port_enabled true if port is enabled. (see table 60 on page 102 ). link_enabled true if link detection is enabled (see table 58 on page 102 .) link_ok true if link is enabled and link is detected or if link detection is disabled. always true for mii port. port_partitioned true if port has been auto partitioned (10mb mode). true if port has been auto partitioned or isolated (100mb mode). port_is_tp true if port is a twisted-pair port. rps_present true if redundant power supply is switched in. rps_fault true if redundant power supply has a fault. port_ctl_hw true if configuration bits are set to hardware control. port_ctl_off true if configuration bits are set to turn off the led. port_ctl_on true if configuration bits are set to turn on the led solid. port_ctl_fast true if configuration bits are set to fast blink the led. rcv_activity true if twisted-pair port on this device is receiving a packet. mgr_present true if mgr_pres signal is active.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 44 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.7.6.1 led mode 1 mode 1 operations are described in table 15 . table 15. led mode 1 indications led operating mode hardware control 1 software control on blink off port n led1 10 mbps operation link_ok, not port_partitioned n/a any other state off via port led control register 100 mbps operation port n led2 10 mbps operation link_ok, port_partitioned 100 mbps operation port n led3 auto- negotiate enabled autoblink active 100 mbps link_ok not link_ok (fast blink) 10 mbps link_ok autoblink inactive n/a auto-negotiate disabled 100 mbps mode selected link_enabled n/a 10 mbps mode selected link_enabled collision and activity leds any the collision and activity leds are on a per segment basis. pulse stretchers are used to extend the on- time for the leds. for every on- cycle of the stretched leds, an off-cycle, with the same period as the on-cycle, always follows. the collision leds turn on for approximately 120 s when the lxt98x0 detects a collision on the segments. during the time that the led is on, any additional collisions are ignored by the collision led logic. the activity leds turn on for approximately 4 ms when the lxt98x0 detects any activity on the segments. during the time that the led is on any additional activity is ignored by the activity led logic. global fault any any port_partitioned or rps_fault and rps_present n/a any other state rps fault any rps_present, rps_fault n/a manager present any mgr_present n/a not mgr_present 1. refer to table 13: led terms, which defines all key terms used in this section.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 45 3.7.6.2 led mode 2 mode 2 operations are described in table 16 . table 16. led mode 2 indications led operating mode hardware control 1 software control on blink off port n led1 any 10 mbps: port_enabled, link_ok, not port_partitioned 100 mbps: port_enabled, link_ok, not port_partitioned 10 mbps: port_enabled, link_ok, and port_partitioned (slow blink) 100 mbps: port_enabled, port_partitioned (slow blink) any other state on, off or fast blink via port led control register port n led2 rcv_activity (20 ms pulse) 2 n/a any other state n/a port n led3 auto- negotiate enabled autoblink active 100 mbps link_ok no link_ok (fast blink) 10 mbps link_ok off via port led control register autoblink inactive n/a auto-negotiate disabled 100 mbps mode selected (link_enabled) 10 mbps mode selected (link_enabled) collision and activity leds any the collision and activity leds are on a per segment basis. pulse stretchers are used to extend the on- time for the leds. for every on-cycle of the stretched leds, an off-cycle, with the same period as the on- cycle, always follows. the collision leds turn on for approximately 120 s when the lxt98x0 detects a collision on the segments. during the time that the led is on, any additional collisions are ignored by the collision led logic. the activity leds turn on for approximately 4 ms when the lxt98x0 detects any activity on the segments. during the time that the led is on, any additional activity is ignored by the activity led logic. n/a manager present any n/a n/a always off n/a rps rps_present, no rps_fault rps_present, rps_fault (slow blink) not rps_present n/a global fault n/a any port_partitioned, any port isolated or rps_fault and rps_present (slow blink) any other state on, off, or slow blink via global led control register 1. refer to table 14 : led terms, which defines all key terms used in this section. 2. receive activity is stretched to a 20 ms wide pulse. for every on-cycle of the stretched leds, an off-cycle, with the same period as the on-cycle, always follows.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 46 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.7.6.3 led mode 3 mode 3 operations are described in table 17 . table 17. led mode 3 indications led operating mode hardware control software control on blink off port n led1 10 mbps operation link_ok, not port_partitioned n/a any other state off via port led control register 100 mbps operation port n led2 10 mbps or 100 mbps ops rcv_activity (20 ms pulse) 2 n/a any other state n/a port n led3 auto- negotiate enabled autoblink active 100 mbps link_ok no link_ok (fast blink) 10 mbps link_ok off via port led control register autoblink inactive 100 mbps mode selected (link_enabled) n/a 10 mbps mode selected (link_enabled) auto-negotiate disabled collision and activity leds any the collision and activity leds are on a per segment basis. pulse stretchers are used to extend the on-time for the leds. for every on-cycle of the stretched leds, an off-cycle, with the same period as the on-cycle, always follows. the collision leds turn on for approximately 120 s when the lxt98x0 detects a collision on the segments. during the time that the led is on, any additional collisions is ignored by the collision led logic. the activity leds turn on for approximately 4 ms when the lxt98x0 detects any activity on the segments. during the time that the led is on, any additional activity is ignored by the activity led logic. n/a global fault any any port_partitioned or rps_fault and rps_present n/a any other state off via global led control register rps fault rps_present, rps_fault n/a manager present mgr_present n/a not mgr_present n/a 1. refer to table table 14 : led terms, which defines all key terms used in this section. 2. receive activity is stretched to a 20 ms wide pulse. for every on-cycle of the stretched leds, an off-cycle, with the same period as the on-cycle, always follows.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 47 3.7.6.4 led mode 4 mode 4 operations are described in table 18 . 3.8 irb operation the inter-repeater backplane (irb) allows multiple devices to operate as a single logical repeater, exchanging data and collision status information. each segment on the lxt98x0 has its own complete, independent irb. the backplanes use a combination of digital and analog signals as shown in figure 9 on page 50 . table 18. led mode 4 indications led operating mode hardware control 1 software control on blink off port n led1 10 mbps operation link_ok, not port_partitioned 20 ms blink indicates rcv_activity 2 any other state off via port led control register 100 mbps operation any other state port n led2 10 mbps operation link_ok, port_partitioned n/a any other state 100 mbps operation port n led3 auto- neg enabled autoblink active 100 mbps link_ok no link_ok (fast blink)) 10 mbps link_ok autoblink inactive n/a auto-neg disabled 100 mbps mode selected (link_enabled) 10 mbps link_enabled collision and activity leds any the collision and activity leds are on a per segment basis. pulse stretchers are used to extend the on-time for the leds. for every on-cycle of the stretched leds, an off-cycle, with the same period as the on- cycle, always follows. the collision leds turn on for approximately 120 s when the lxt98x0 detects a collision on the segments. during the time that the led is on, any additional collisions are ignored by the collision led logic. the activity leds turns on for approximately 4 ms when the lxt98x0 detects any activity on the segments. during the time that the led is on, any additional activity is ignored by the activity led logic. n/a global fault any any port partitioned or rps_fault and rps_ present n/a any other state off via global led control register rps fault rps_fault and rps_ present n/a manager present mgr_present n/a not mgr_present 1. refer to table 14 : led terms, which defines all key terms used in this section. 2. receive activity is stretched to a 20 ms wide pulse. for every on-cycle of the stretched leds, an off-cycle, with the same period as the on-cycle, always follows.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 48 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.8.1 irb signal types irb signals can be characterized by the following connection types (for stacking and cascading connections, see table 19 on page 50 ): local ? connected between devices on the same board stack ? connected between boards full ? connected between devices in the same board and between boards. 3.8.2 irb isolation the isolate outputs (ir10iso and ir100iso) are provided to control the enable pins of external bidirectional transceivers. in stacking applications, they can be used to isolate one board from the rest of the stack. only one device can control these signals. the output states of these pins are controlled by the isolate bits in the repeater configuration register. 3.8.3 10 mbps-only operation 3.8.3.1 mac irb access the macactive pin allows an external mac or other digital asic to interface directly to the 10 mbps irb. when the macactive pin is asserted, the lxt98x0 drives the ir10cfs and ir10cfsbp signals on behalf of the external device, allowing it to participate in collision detection functions. 3.8.3.2 management master chain arbitration this daisy chain is provided for correct statistics gathering in 10 mbps cascaded configurations. in stacked applications, this daisy chain must be maintained through cascades. in stand-alone applications, or for the first device in a chain, the mmstrin input must be pulled low for the management counters to work correctly. 3.8.4 lxt98x/91x/98x0 compatibility the lxt98x0 devices feature low-power 3.3v design. the lxt98x and lxt91x devices operate at 5v and are incompatible with the lxt98x0 devices in cascades. the lxt98x0 devices, however, are backwards stackable with lxt98x and lxt91x repeaters. note: refer to ? inter-repeater backplane compatibility ? on page 71 .
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 49 figure 8. 100 mbps irb connection ir100dat(4:0) ir100dv ir100clk ir100cfs ir100dat(4:0) ir100dv ir100clk ir100cfsbp hub #1 hub #2 74lvt245 74lvt245 ir100den ir100den ir100sngl ir100col ir100cfs ir100sngl ir100col lxt98x0 lxt98x0 (00) lxt98x0 (00) lxt98x0 cascade stack
lxt9860/9880 ? advanced 10/100 repeater with integrated management 50 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 figure 9. irb block diagram table 19. cascading and stacking connections signal type connections between devices (cascading) connections between boards (stacking) local connect all. do not connect. stack for devices with chipid 00, pull-up at each device and do not interconnect . connect devices with chipid = 00 between boards. use one pull-up resistor per stack. full connect all. connect using buffers. special (xxiso) for devices with chipid 00, leave open. for device with chipid = 00, connect to buffer enable. do not connect. mmstr out mmstr out digital irb signals include irndat, irncol, ir10colbp, irnena and irnclk. local analog irb signal: irncfs. inter-board analog irb signal: irncfsbp. this diagram shows a single irb. the lxt98xx actually has two independent irbs, one per speed/segment. ? 245 9880 chipid = 0 9880 chipid = 1 9880 chipid = n hub board 1 digital irb signals analog irb signals mmstr out / in mmstr out / in mmstr out mmstr in isolate irden holdcol ? 245 988 chipid = 0 9880 chipid = 1 9880 chipid = n hub board 2 digital irb signals analog irb signals mmstr out / in mmstr out / in mmstr out mmstr in isolate irden holdcol ? 245 9880 chipid = 0 9880 chipid = 1 9880 chipid = n hub board n digital irb signals analog irb signals mmstr out / in mmstr out / in mmstr out mmstr in isolate irden holdcol mmstr out / in holdcol, mmstrin, and mmstrout are used on the 10m irb only.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 51 3.9 mii port operation the lxt98x0 mii ports allow direct connection with a mac. the mii ports can operate at either 10 mbps or 100 mbps. speed control is provided via mii n_ spd. for 100 mbps operation, set mii n _spd = 1. for 10 mbps operation, set mii n_ spd = 0. the lxt98x0 maintains the same statistics for the miis as it does for the 10/100 ports (except for isolate, partition, and illegal symbols). the lxt98x0 does not provide mdio/mdc capability, as this is provided via the serial management interface (smi). 3.9.1 preamble handling when operating at 100 mbps, the lxt98x0 passes the full 56 bits of preamble through before sending the sfd. when operating at 10 mbps, the lxt98x0 sends data across the mii starting with the 8-bit sfd (no preamble bits). note: mii ports do not count partition, isolation, or symbol errors. table 20. irb signal details name pad type buffer pull-up connection type 100 mbps irb signals ir100dat<4:0> digital yes no full ir100clk digital yes 1k full ir100dv digital, open drain yes 300 ? full ir100cfs analog no 215 ? , 1% local ir100cfsbp analog no 91 ? , 1% stack ir100col digital no no local ir100sngl digital no no local ir100den digital, open drain n/a 1 330 ? local ir100iso digital n/a 1 no special 10 mbps irb signals ir10dat digital, open drain yes 330 ? full ir10clk digital yes no full ir10ena digital, open drain yes 330 ? full ir10cfs analog no 215 ? , 1% local ir10cfsbp analog no 330 ? , 1% stack ir10col digital no 330 ? , 1% local ir10colbp digital no 330 ? , 1% stack ir10den digital, open drain n/a 1 330 ? local ir10iso digital n/a 1 no special 1. isolate and driver enable signals are provided to control an external bidirectional transceiver.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 52 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.10 serial management i/f the high-speed serial management interface (smi) provides access to repeater mib variables, rmon statistics attributes and status and control information. a network manager accesses the interface through a simple serial communications controller such as an 8530 scc. the smi allows multiple lxt98x0 devices to be managed from one common bus. 3.10.1 smi signals the interface consists of a data input line (srx), data output line (stx), and a clock (serclk). the interface operates on a simple command response model, with the network manager as the master and the lxt98x0 devices as slaves. figure 11 is a simplified view of typical serial management interface architecture. refer to figure 23 on page 68 for circuit details. note: refer to application note 64, high-speed serial management interface, for additional information. figure 10. lxt9880 mii operation mii n _txd<3:0> mii n _txen mii n _txer mii n _txclk mii n _rxclk mii n _rxd<3:0> mii n _rxdv mii n _rxer mii n _crs mii n _col lxt98x0 10/100 mac the two lxt98x0 mii ports act as the phy side of the mii. an external mac sends tx data to the lxt98x0 to be repeated to the network. the lxt98x0 repeats network data to the mac via the rx data lines. port 1 port 2 port 3 port 4 ports 1, 2 tp ports mii ports port 6 port 7 port 8 port 5 figure 11. typical smi bus architecture lxt918 lxt918 lxt9880 rmon & repeater mib support serial controller network management user definable partitioning
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 53 3.10.1.1 serial clock serclk is a bidirectional pin; direction control is provided by the reconfig input. if reconfig is high, the lxt98x0 drives serclk at 625 khz. if reconfig is low, serclk is an input, between 0 and 2 mhz. the clock can be stopped after each operation, as long as an idle (at least 12 ones in a row) is transmitted first. 3.10.1.2 serial data i/o the serial data pins, srx and stx, should be ? logically ? tied together using open-collector buffers. see figure 23 on page 68 . the srx input is compared with the stx output. if a mismatch occurs, stx goes to a high impedance. stx is driven on the falling edge of serclk. srx is sampled on the rising edge. 3.10.2 read and write operations data can be read or written in blocks. the lxt98x0 can read the full length field of consecutive counters with a single access. block writes are limited to 2 long words. normally the network manager directs read and write operations to a specific lxt98x0 device using a two-part address consisting of hubid and chip address. note: in the header field, the chip address is defined by three bits. the most significant bit (msb) = 0; the value of the other two bits is set by pins. the lxt98x0 responds to an operation within 12 serial controller bit times. in the case of an error during a transfer, the lxt98x0 does not implement the requested command. 3.10.2.1 smi collision handling upon colliding with another packet, the lxt98x0 ceases transmission, based on the bit pattern of the colliding packets as shown in figure 12 . in the case of a collision, the driver who is sourcing a 0 wins. the lxt98x0 does not retry a response, unless it was an address arbitration packet. in addition, if an address arbitration packet jumps in during a request/response sequence, before the addressed lxt98x0 has responded, the addressed lxt98x0 aborts the requested operation. note: the minimum time between packets must be at least 12 bit times with the data set to all ones. 3.10.2.2 smi address match indication the lxt98x0 ser_match pin (see figure 13 ) indicates detection of a serial command matching the device hub id. broadcast commands also trigger the ser_match output. note that the initial hubid upon power-up or reset is the broadcast (all ones) address.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 54 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.10.2.3 smi frame format the smi uses a simple frame format, shown in figure 14 . table 21 describes the individual fields. table 22 shows how the bits for the header field are stored in memory, assuming that they are transmitted lsb to msb, low address to high address. table 23 lists the command set and table 24 provides a variety of typical packets. all frames begin and end with a simple flag consisting of ? 01111110 ? . multiple flags cause the lxt98x0 to ignore the packet. all fields are transmitted lsb first. zero-bit stuffing is required if more than five 1s in a row appear in the header, data or crc fields. in addition, all operations directed to the device must be followed by an idle (at least 12 ones in a row), and the first operation must be preceded with an idle. note: the lxt98x0 uses the ccitt method of crc (x 16 + x 12 + x 5 +1). figure 12. smi collision handling figure 13. smi address match indication pkt 1-succeeds pkt 2-ceases, due to collision pkt 3-ceases, due to collision data data data clk 1. simultaneous transmissions, pkt 1 completes transmit om falling clk edge, sample on rising clk edge. hub id chip id, etc. srx/stx ser_match serclk 1. ser_match can also occur at the end of a packet if a start flag is not seen but a stop flag is. this can occur only during unit installation or removal.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 55 table 21. smi message fields message description start or stop flag ? 01111110 ? . protocol requires zero insertion after any five consecutive ? 1 ? s in the data stream. hub id identifies board or sub-system. assigned by one of two arbitration mechanisms at power- up. chip id identifies one of eight devices on a system. assigned by 2 external pins on each device. the most significant bit (msb) = 0; the value of the other two bits is set by pins. command identifies the particular operation being performed (see table 23 ) length specifies number of registers to be transferred (1 to 127). maximum is 2 per write, 127 per read. address specifies address of register or register block to be transferred. figure 14. serial management frame format table 22. smi header storage msb lsb increasing address addr 11 addr 10 addr 9 addr 8 addr 7 addr 6 addr 5 addr 4 addr 3 addr 2 addr 1 addr 0 length 6 length 5 length 4 length 3 length 2 length 1 length 0 cmd 4 cmd 3 cmd 2 cmd 1 cmd 0 chip address bit 2 (set to 0) chip address bit 1 chip address bit 0 hubid 4 hubid 3 hubid 2 hubid 1 hubid 0 hub id chip add cmd length 7 bits address 12 bits data (0-508 bytes) start flag header crc (2 bytes) stop flag idle idle header content: 5 bits 3 bits 5 bits
lxt9860/9880 ? advanced 10/100 repeater with integrated management 56 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 23. smi command set command value name usage normally sent by description 18 (hex) write normal ops network mgr used to set a register or group of registers. the minimum write size is 1 long word. the maximum block write is 2 long words. this size was chosen so that software may write an entire ethernet address in one serial packet. 04 (hex) read normal ops network mgr used to get complete sets of counter information for either a port or a segment. the minimum read size is 32 bits (one long word). the maximum block read is 127 long words. the acknowledge for this instruction is the actual returned data. 08 (hex) request id arbitration lxt98x0 for hub id (arb method 1): the lxt98x0 repeats this command periodically until it is assigned a hub id. once assigned, the command is discontinued. 00 (hex) configchg arbitration lxt98x0 notifies system of configuration change (hot swap). requests new arbitration phase. 10 (hex) re-arbitrate arbitration network mgr re-starts arbitration. assigns all new addresses. 14 (hex) assign hubid chain arbitration network mgr assigns hub id to device with arbin = 0 and arbout = 1 0c (hex) set arbout to 1 chain arbitration network mgr used to determine stacking order or assign address. commands specific device to set arbout= 1. this command can apply to either a single lxt98x0 (via direct addressing), or every lxt98x0 through the use of the broadcast address. 1c (hex) set arbout to 0 chain arbitration network mgr used to determine stacking order or assign address. commands specific device to set arbout = 0. this command can apply to either a single lxt98x0 (via direct addressing), or every lxt98x0 through the use of the broadcast address. 02 (hex) devid config network mgr asks device to send contents of device revision register. this command applies to only a single lxt98x0 at a time. when given, the command causes the chip to retrieve its type and revision code data (hard coded for a given device) and provide it to the serial controller for transmission back to the requesting manager. the acknowledge for this type of packet is the actual returned data. this command can also be used for ? ping ? operations.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 57 3.10.3 address assignment methods each device has a two part address, consisting of a hubid and a chip address (see figure 14 on page 55 ). the chip address is assigned by the input pins chipid<1:0>. (the most significant bit [msb] = 0.) the manager assigns the hubid. each lxt98x0 on a particular board has the same hubid. the hubid is assigned through one of two arbitration mechanisms as shown in figure 15 . table 24. typical serial management packets message contents of fields in serial management packet hub id chip address 5 command length address data write 1, 2 user defined user defined 18 hex 01 or 02 hex user defined user defined read request 1, 3, 4 user defined user defined 04 hex 01 to 7f hex user defined null read response 3 00000 000 04 hex 01 to 7f hex user defined data values assign hub id (arb method 1) 11111 011 18 hex 02 hex 188 hex formatted per table 89 on page 115 and table 90 on page 116 assign hub id (arb method 2) 11111 011 14 hex 01 hex 000 hex hub id (lsb) and 27 0s set arbout to 0 user defined user defined 1c hex 00 hex 000 hex null set arbout to 1 user defined user defined 0c hex 00 hex 000 hex null arb request 00000 000 08 hex 02 hex 190 hex prom id resend arbitration 11111 011 10 hex 00 hex 000 hex null resend arbitration response 00000 000 08 hex 02 hex 190 hex prom id device type/ revision code user defined user defined 02 hex 01 hex 000 hex null device/revision response 00000 000 02 hex 01 hex 13c hex device type/ revision 1. other than checking that the top 3 bits of the address equals 000, the lxt98x0 does not check if the user writes or reads past the highest location. there are no adverse effects for writing or reading locations above the specified range. 2. if the user performs a write operation of length 1 or 2 and does not send a data field, the lxt98x0 writes junk into the specified registers. this constitutes an invalid command. 3. if the user reads past the highest location of the lxt98x0, all those locations reads back 0s. 4. if a read operation is performed with a length of 0, the lxt98x0 does not respond. 5. chipid is defined by 3 bits, with the msb = 0; value of the other two bits is set by pins.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 58 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.10.3.1 chain arbitration mechanism the chain method is the easiest and requires no serial prom. the arbselect pin on all devices must be set to 1. when constructing the stack, the designer creates a daisy chain by tying the arbout pin of each lxt98x0 to the arbin pin of the following lxt98x0. the manager is at the top of the stack and controls the arbin for the first lxt98x0. the manager progressively assigns hub ids using the assign hub id (arb method 2) and set arbout to zero commands. the manager initially sets its arbout (first lxt98x0 ? s arbin) to zero. since the assign hub id (arb method 2) command only works on the lxt98x0 with arbin of 0 and an arbout of 1, the first lxt98x0 can be assigned an address. after the first lxt98x0 has been assigned an address, it can uniquely be told to switch its arbout to zero. this creates the (01) condition on the next lxt98x0 in the line. this lxt98x0 is then assigned an address and the process continues until all chips have been assigned a unique address. note: it is recommended that hubids match in any given hub. the manager can verify that a hub is still present by performing device id commands. if a change of configuration is detected, the manager can perform a broadcast write to return each hub ? s arbout to 1, and then re-perform the address assignment process. when using the chain arbitration method, set up the daisy chain so the device with chipid = 00 is the first device in the board that the chain passes through. when assigning ids, the ? 1st in chain ? bit in the device revision register (refer to table 77 on page 111 ) can be used to determine when a new board has been encountered. 3.10.3.2 prom arbitration mechanism this mechanism requires one serial prom with a unique 48-bit id in each board. this id can consist of serial number, date/week/year of manufacture, etc. the arbselect pin must be set to 0. at power-up, the device with chipid = 00 reads a 48-bit id from the prom. all other devices figure 15. address arbitration mechanisms 1 lxt98x0 arbin arbout network manager arbout serial i/f to next module srx/stx lxt98x0 arbin arbout srx/stx 0 srx/stx hub board 1 1 lxt98x0 arbin arbout srx/stx 1 lxt98x0 arbin arbout srx/stx 0 hub board 2 arbi/o chain to next module 0 chain mechanism for address arbitration network manager serial i/f to next module srx/stx hub board 1 serial eprom lxt98x0 srx/stx promdti/o lxt98x0 srx/stx promdti/o hub board 2 serial eprom lxt980 srx/stx promdti/o lxt980 srx/stx promdti/o eprom mechanism for address arbitration
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 59 on the board listen in and record the id. the device with chipid = 00 then transmits arbitration request messages on the smi every 2-3 ms. the request messages from two boards may collide. if this happens, a resolution scheme ensures that only one message is transmitted. the network manager must respond to each request with a message that includes the 48-bit id and the hubid. all devices hear this message, but only those matching the 48-bit id receive the hubid as their own. once a hubid is assigned to a hub, that hub ceases requesting a hubid. this process continues until all hubs are assigned an id. should a hub power off and back on, the hub re- requests an id, which the manager provides. an address arbitration packet is selected over normal requests. 3.10.3.3 address re-arbitration there are two mechanisms for address re-arbitration following a configuration change, such as a hot-swap of a board: manual re-arbitration. if the lxt98x0 detects a low-to-high transition on reconfig, or if reconfig is high at power-up, it sends out a ? configuration change ? message (start flag with all 0s) on the bus. the network manager can use this message to detect that re-arbitration is required. network manager. the network manager can detect or re-start arbitration at any time by sending the ? re-arbitrate ? command. 3.10.4 interrupt functions the lxt98x0 provides a single open-collector pin for external interrupt signalling. several different interrupt conditions may be reported. the interrupt status register (see table 86 ) identifies the specific interrupt condition. the interrupt mask register (see table 87 on page 115 ) allows specific interrupts to be masked. interrupts may be cleared in two ways, depending on the status of bit 11 in the repeater configuration register. 3.11 serial prom interface the serial prom interface allows the vendor to load in optional information unique to each board. items such as serial number or manufacture date can be placed in the serial prom which can also be used in the address arbitration process. each board must contain a unique set of information. additionally, only 1 serial prom is required per board, they are not required per chip. the lxt98x0 reads in the first 48 bits (three 16-bit words) from the prom and stores them in a register. this read occurs only on power-up. only the lxt98x0 with a chipid of 00 drives the serial prom control lines; all other lxt98x0s ? listen ? to the data and clock lines. the first bit into the lxt98x0 from this interface corresponds to bit 47. the serial prom shifts out the most significant bit (15) of the word first (the prom must be auto-incrementing).
lxt9860/9880 ? advanced 10/100 repeater with integrated management 60 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 3.12 serial configuration interface the serial configuration interface allows the user to load system-specific information (board type, plug-in cards, status, etc.) into the repeater configuration register (see table 75 on page 109 ). this register may be read remotely through the serial management interface (smi). the serial configuration interface mode (repeater configuration register bit 14 = 1) allows the collection of up to 8 bits of board data, compared to the config[1:0] 2-bit mode (bit 14 = 0). see table 75 on page 109 . for serial configuration interface mode = 1, an external ? 165 device is used to perform a parallel- to-serial conversion of the board data (see figure 17 ). these board data bits are shifted into the lxt98x0 each time the repeater serial configuration register is read. cfg_dt is clocked into the lxt98x0 relative to the rising edge of cfg_clk as shown in figure 18 . also note the register bit positions versus the ? 165 parallel input positions. the cfg_clk pin is shared with led_clk. for reading the repeater serial configuration register, the configuration bits are reloaded into the lxt98x0. the shared functionality of the clock (configuration and serial led), causes an unscheduled serial led update. all 32 clock cycles occur with only the first 8 bits clocked into the repeater serial configuration register. see table 76 on page 110 . figure 16. optional r/w serial prom interface clk dtout the lxt98x0 drives outgoing data on the falling clock edge. the lxt98x0 samples incoming data on the rising clock edge . cs
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 61 4.0 application information 4.1 general design guidelines following generally accepted design practices is essential to minimize noise levels on power and ground planes. up to 50 mv of noise is considered acceptable. 50 to 80 mv of noise is considered marginal. high-frequency switching noise can be reduced, and its effects can be eliminated, by following these simple guidelines throughout the design: fill in unused areas of the signal planes with solid copper. attach them with vias to a vcc or ground plane that is not located adjacent to the signal layer. use ample bulk and decoupling capacitors throughout the design (a .01 f value is recommended for decoupling caps). provide ample power and ground planes. provide termination on all high-speed switching signals and clock lines. provide impedance matching on long traces to prevent reflections. route high-speed signals next to a continuous, unbroken ground plane. filter and shield dc-dc converters, oscillators, etc. figure 17. serial configuration interface figure 18. serial configuration interface signaling ?165 cfg_clk cfg_dt lxt98x0 cfg_ ld clk q h sh/ ld a b c d e f g h parallel config. data ser cfg_ ld cfg_dt g = b1 f = b2 e= b3 d = b4 c = b5 b = b6 a = b7 cfg_clk 100 ns / 10 mhz h = b0
lxt9860/9880 ? advanced 10/100 repeater with integrated management 62 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 do not route any digital signals between the lxt98x0 and the rj-45 connectors at the edge of the board. do not extend any circuit power and ground plane past the center of the magnetics or to the edge of the board. use this area for chassis ground, or leave it void. 4.2 typical applications figure 19 and figure 20 are simplified block diagrams showing typical applications. figure 21 through figure 26 show application circuitry details. figure 19. 8-port managed 10/100 stackable repeater figure 20. 32-port managed 10/100 repeater serial comm controller bridge 10m mac 100m mac 74lvt245 8 10/100 ports serial port 10m irb 100m irb tp ports mii 2 mii 1 74lvt245 serial comm controller bridge 10m mac 100m mac 74lvt245 32 10/100 ports serial port 10m irb 100m irb tp ports mii 2 mii 1 serial port 10m irb 100m irb tp ports mii 2 mii 1 serial port 10m irb 100m irb tp ports mii 2 mii 1 serial port 10m irb 100m irb tp ports mii 2 mii 1 rmon (optional 10m or 100m mac 74lvt245
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 63 4.3 application circuitry 4.3.1 power and ground 4.3.1.1 supply filtering power supply ripple and digital switching noise on the vcc plane causes emi and degrades line performance. predicting a design ? s performance is difficult, although certain factors greatly increase the risks: poorly-regulated or over-burdened power supplies. wide data busses (>32-bits) running at a high clock rate. dc-to-dc converters. many of these issues can be improved by following good general design guidelines. in addition, intel recommends filtering between the power supply and the analog vcc pins of the lxt98x0. filtering has two benefits. first, it keeps digital switching noise out of the analog circuitry inside the lxt98x0, which helps line performance. second, if the vcc planes are laid out correctly, it keeps digital switching noise away from external connectors, reducing emi. the vcc plane should be divided into two sections. the digital section supplies power to the digital vcc pins and to the external components. the analog section supplies power to vccr and vcct pins of the lxt98x0. the break between the two planes should run under the device. in designs with more than one lxt98x0, use a single continuous analog vcc plane to supply them all. the digital and analog vcc planes should be joined at one or more points by ferrite beads. the beads should produce at least a 100 ? impedance at 100 mhz. the beads should be placed so current flows evenly. the maximum current rating of the beads should be at least 150% of the current that is actually expected to flow through them. each lxt98x0 draws a maximum of 1000ma from the analog supply so beads rated at 1500ma maximum should be used. a bulk cap (2.2 -10 f) should be placed on each side of each ferrite bead to ground to stop switching noise from traveling through the ferrite. in addition, a high-frequency bypass cap (.01 f) should be placed near each analog vcc pin to ground. 4.3.1.2 ground noise the best approach to minimize ground noise is strict use of good general design guidelines and by filtering the vcc plane. 4.3.1.3 power and ground plane layout considerations the power and ground planes should be laid out carefully. the following guidelines are recommended: follow the guidelines in the application note 113 (lxt98x0 design and layout guide) for locating the split between the digital and analog vcc planes. keep the digital vcc plane away from the tpop/n and tpip/n signals, magnetics, and rj-45 connectors.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 64 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 place the layers so the tpop/n and tpip/n signals are routed near or next to the ground plane. for emi, it is more important to shield tpop/n than tpip/n. 4.3.1.4 chassis ground for esd protection, create a separate chassis ground. for isolation, encircle the board and place a ? moat ? around the signal ground plane to separate signal ground from chassis ground. chassis ground should extend from the rj-45 connectors to the magnetics, and can be used to terminate unused signal pairs ( ? bob smith ? termination). in single-point grounding applications, provide a single connection between chassis and circuit grounds with a 2kv isolation capacitor. in multi- point grounding schemes (chassis and circuit grounds joined at multiple points), provide 2kv isolation to the bob smith termination. 4.3.1.5 the rbias pin the lxt98x0 requires a 22.1 k ?, 1% resistor directly connected between the rbias pin and ground. place the rbias resistor as close to the rbias pin as possible. run an etch directly from the pin to the resistor, sink the other side of the resistor, and surround the rbias trace with a filtered ground. do not run high-speed signals next to rbias .
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 65 4.3.2 mii terminations the lxt98x0 miis have high output impedance (250-350 ? ). to minimize reflections, serial termination resistors are recommended on all mii signals, especially with designs with long traces (>3 inches). place the resistor as close to the device as possible. use a software trace termination package to select an optimal resistance value for the specific trace. proper value = nominal trace impedance minus 13 ? . if a software package cannot be used and nominal trace impedance is not known, use 55 ? . 4.3.3 twisted-pair interface the lxt98x0 transmitter uses standard 1:1 magnetics for both receive and transmit. nonetheless, system designers should take precautions to minimize parasitic shunt capacitance and meet return loss specifications. these steps include: figure 21. power and ground connections rbias vcc gnd gnd vccr gnd .01 f 22.1 k ? 1% gnd vcc 0.1 f + ferrite beads 10 f +3.3v lxt9880 vcct gnd 10 f .01 f .1 f .1 f digital supply plane analog supply plane .01 f .1 f to output magnetics centertap
lxt9860/9880 ? advanced 10/100 repeater with integrated management 66 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 place magnetics as close as possible to the lxt98x0. keep transmit pair traces short. do not route transmit pair adjacent to a ground plane. eliminate planes under the transmit traces completely. otherwise, keep planes 3-4 layers away. improve emi performance by filtering the output center tap supply. a single ferrite bead may be used in the center tap supply to all ports. a ferrite bead with a total maximum current rating of 1.5amp is recommended. place 270pf 5% capacitors at tpip and tpin to improve signal-to-noise immunity at the receiver, especially for long line lengths. in addition, follow all the standard guidelines for a twisted-pair interface: route the signal pairs differentially, close together. allow nothing to come between them. keep distances as short as possible; both traces should have the same length. avoid vias and layer changes. keep the transmit and receive pairs apart to avoid cross-talk. to provide maximum isolation, place entire receive termination network on one side and transmit on the other side of the pcb. bypass common-mode noise to ground on the in-board side of the magnetics using 0.01 f capacitors. keep termination circuits grouped closely together and on the same side of the board. always put termination circuits close to the source end of any circuit. 4.3.3.1 magnetics information the lxt98x0 requires a 1:1 ratio for the receive transformers and a 1:1 ratio for the transmit transformers. the transformer isolation voltage should be rated at 2 kv to protect the circuitry from static voltages across the connectors and cables. refer to table 25 for magnetics specifications. 4.3.4 clock a stable, external 25 mhz system clock source (cmos) is required. see table 26 . table 25. lxt98x0 magnetics specifications parameter min nom max units test condition rx turns ratio ? 1 : 1 ?? tx turns ratio ? 1 : 1 ?? insertion loss 0.0 ? 1.1 db 80 mhz primary inductance 350 ?? h transformer isolation ? 2 ? kv differential to common mode rejection -40 ? db .1 to 60 mhz -35 ? db 60 to 100 mhz return loss - standard -16 ? db 30 mhz -10 ? db 80 mhz
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 67 table 26. oscillator manufacturers manufacturer part number frequency cts mxo45 / 45lv 25 mhz epson america sg-636 series 25 mhz figure 22. typical twisted-pair port interface and power supply filtering tpfip tpin rj45 tpop tpon vcct gnd 0.1 f .01 f 50 ? 1% to twisted-pair network 3 6 1 2 1:1 1:1 lxt98x3 50 ? 50 ? 50 ? 50 ? 50 ? 50 ? 4 5 8 7 50 ? 1% 0.01 f 5% 270 pf 5% 270 pf 5% 0.001 f 2kv 0.001 f 2kv 0.001 f 2kv tpip .01 f
lxt9860/9880 ? advanced 10/100 repeater with integrated management 68 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 4.3.5 smi and prom circuits figure 23. typical serial management interface connections figure 24. serial controller connection showing pal vcc 74xx05 srx stx 1. when not transmitting stx goes to 1, hence open collector and no drive. 8530 rxda txda rtxca ctsa oc driver clk serial line pal rtsa 1. pal is used to detect collisions and gate (cease) transmission. the pal notifies the 8530 to abort the current transmission via the cts bit, which is then cleared by the rts bit.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 69 4.3.6 led circuits 4.3.6.1 direct drive leds each direct drive led has a corresponding open-drain pin. the leds are connected, via a current limiting resistor, to a positive voltage rail. the leds are turned on when the output pin drives low. the open-drain led pins are 5v tolerant, allowing use of either a 3.3v or 5v rail. a 5v rail eases led component selection by allowing more common, high forward voltage leds to be used. refer to figure 27 for a circuit illustration. 4.3.6.2 led pins multiplexed with configuration inputs some static configuration inputs are multiplexed with led pins to reduce the lxt98x0 pin count. these led pins are configured by current sinking (open- drain output) and sourcing (open-source output). if the led pin sinks the led current, the configuration value is ? 1 ? . if led pin sources figure 25. serial prom interface figure 26. typical reset circuit 93cs46 prom_cs prom_clk prom_dtin prom_dtout prom_dtin prom_clk lxt98x0 (id = 00) lxt98x0 (id 00 ) vcc c r1 r2 ? 14 d 1. t(cr1 > power supply ramp up time. r2 discharges c when supply goes away. the ? 14 is needed for multiple lxt98x0 devices.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 70 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 the current, the configuration value is a ? 0 ? . the lxt98x0 detects the configuration value following reset and then selects the appropriate output drive circuit (open drain or source). if the led function of a multiplexed configuration pin is not used, tie the pin to ground or vcc via a 100 ? 500 k ? resistor to set the configuration value. multiple led configuration pins can be tied off with a single resistor to set them all to the same value. refer to figure 27 for a circuit illustration. for configuration values of ? 1 ? , a 3.3v or a 5v rail can be used to drive the leds (to ease led selection as with direct drive leds). for configuration values of ? 0 ? , external buffering is used when 5v led driving is desired. (this buffering could be as simple as a single transistor.) as an alternative, use the copies of the multiplexed led data found on the led serial interface. if a 5v tolerant serial-to-parallel device is used for the led serial interface, 5v led driving is achieved (see ? serial leds ? on page 70 ). 4.3.6.3 serial leds the lxt98x0 provides a serial interface to support additional led options. standard shift registers, either 74x595s (8-bit serial-to-parallel with output registers) or 74x164s (8-bit s/p without registers) can be used to drive these additional leds. collision10/100 and activity10/100 status indications are provided on multiplexed configuration pins and duplicated on the serial port. the led serial interface consists of three outputs: clock (ledclk), parallel latch clock (ledlat), and output data (leddat). the parallel latch clock is used only with the 74x595 implementation. refer to figure 28 for an illustration of the led serial interface circuit. potentially, 30 leds can be driven by the led serial interface via 4 s/p devices. the s/p serial output is connected to the serial input of the first serial input device. to expand the chain, connect the last serial output to serial input of next serial interface device. serial led data is output in the anticipated priority order, from least likely to most likely to be used: unused ? 595/ ? 164 parallel outputs mii ports - led1, 2, 3 figure 27. led circuits - direct drive & multiplexed configuration inputs inside ic outside ic direct drive r v led inside ic outside ic configuration = ? 1 ? inside ic outside ic configuration = ? 0 ? r v led r v led = 3.3 to 5 volts +/- 5% multiplexed multiplexed v cc = 3.3 volts +/- 5% inside ic outside ic configuration = ? 0 ? v cc multiplexed with transistor buffer r v led 100k ? rb v cc
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 71 miscellaneous leds (repeat of collision10/100, manager present, repeat of activity10/100, global fault, rps fault) actgled10 actgled100 this allows the user to leave off devices in the serial-to-parallel chain if the leds associated with that condition aren ? t desired. refer to figure 7 on page 41 which illustrates the led serial interface port signalling and table 12 on page 41 which documents the serial led stream. if the 8 bit serial bus configuration mode is selected (see ? serial configuration interface ? on page 60 .), unscheduled (less than 122 s apart) led serial port cycles occur each time the repeater serial configuration register is read. if the 74x164 buffer is used, flicker is minimized by design so that it is not noticeable to the eye. the led outputs may change momentarily. 4.4 inter-repeater backplane compatibility the inter-repeater backplane (irb) comprises two parts: local ? the backplane between cascaded devices on the same board. stack ? the backplane between multiple boards. each of these backplanes consists of both analog and digital signals. figure 28. serial led circuit ser rclk srclk qa qb . . . qh qh ? led cct. led cct. led cct. r v led led cct. v led side . . . v led = 3.3 to 5 volts +/- 5% 74x595 . . . led cct. led cct. led cct. . . . up to 2 more ? 595s/8xleds leddat ledlat ledclk . . . up to 2 more ? 164s/8xleds led cct. led cct. led cct. v led . . . led cct. led cct. led cct. . . . leddat ledclk qa qb . . . qh a b clk 74x164 qa qb . . . qh a b clk 74x164 actgled100 actgled10 actgled100 actgled10 ser rclk srclk qa qb . . . qh qh ? 74x595 lxt98x0 lxt98x0
lxt9860/9880 ? advanced 10/100 repeater with integrated management 72 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 4.4.1 local backplane ? 3.3v only the lxt98x0 local backplane operates at 3.3v only. lxt98x and lxt91x devices operate at 5v. lxt98x0 devices are, therefore, not cascadable with lxt98x and lxt91x devices. note: do not mix lxt98x0 with either lxt98x or lxt91x devices on the local backplanes. 4.4.2 stack backplane ? 3.3v or 5v the lxt98x0 stack backplanes can be configured to be either 3.3v or 5v. comp_sel (pin 39), a special input pin, selects between the two voltage modes, depending on whether 3.3v or 5v is applied. 3.3v-only stacks apply 3.3v to comp_sel, ir100cfsbp , ir10cfsbp , and ir10colbp for lxt98x0 backplane operation for 5v backwards stackability apply 5v to comp_sel, ir100cfsbp , ir10cfsbp , and ir10colbp for lxt98x and lxt91x backplane operation. with either mode (3.3v or 5v), comp_sel draws less than 3 ma. note: 1. the external pull-up resistor values remain the same, regardless of 3.3v or 5v backplane operation. 2. the recommended digital signal external buffer has been changed to 74lvt245 for the lxt98x0. 4.4.2.1 3.3v and 5.0v stacking boards cannot be mixed 3.3v operation boards designed for 3.3v backplane operation should only be stacked with other 3.3v boards. existing lxt98x or lxt91x based designs cannot operate in 3.3v. incompatible stacking configurations the following stacking configurations are incompatible: a lxt98x0-based board configured for 3.3v backplane operation and lxt98x or lxt91x based boards (5v only). a lxt98x0-based board configured for 3.3v backplane operation and a lxt98x0-based board configured for 5v backplane operation. note: stacking boards designed for 3.3v backplane operation with boards designed for 5v backplane operation causes network errors. 5v operation boards designed for 5v backplane operation should only be stacked with other 5v boards: lxt98x or lxt91x-based designs. lxt98x0 designs configured for 5v backplane operation.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 73 the configuration input must be connected to 5v for compatibility with lxt98x or lxt91x-based designs. the 5v can be supplied from the stacking cable, or a 5v source must exist within the board itself. note: stacking boards designed for 5v backplane operation with boards designed for 3.3v backplane operation causes network errors. figure 29. 100 mbps backplane connection between lxt98x and lxt98x0 ir100dat(4:0) ir100dv ir100clk ir100cfs ir100dat(4:0) ir100dv ir100clk ir100cfsbp hub #1 hub #2 98x0 buffer buffer ir100den ir100den ir100sngl ir100col ir100cfs ir100sngl ir100col (000) (00) 98x0 98x 1. the lxt98x and lxt98x0 devices can share the same inter-repeater backplane so long as the proper backplane buffers are used. configuration is set to 5v. 2. for lxt98x, lxt91x: the buffer should be the 74abt245. for lxt98x0: in the 5v tolerant backplane, the buffer can be either 74abt245 or 74lvt245 3. layout follows the same pattern for 10 mbps operation. 98x 5v 5v
lxt9860/9880 ? advanced 10/100 repeater with integrated management 74 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 figure 30. typical 100 mbps irb implementation figure 31. typical 10 mbps irb implementation lxt98x0 chip id 01 lxt98x0 chip id 10 215 ? 1% 300 ? ir100dv\ ir100dat <4:0> ir100cfs\ ir100col\ ir100sngl ? 245 ir100datbp ir100dvbp\ dir ena ir100clkbp ab lxt98x0 chip id 00 ir100cfsbp\ ir100den\ isolate 91 ? 1%* +3.3v 330 ? ir100clk ir100den\ ir100dv\ ir100dat stack or segment connector ir100cfsbp\ +3.3v 91 ? 91 ? 2 1 1 ? comp_sel +3.3v +3.3v ir100cfsbp\ 1. in stacked configurations, all devices with chipid = 00 are tied together at ir100cfsbp. the entire stack must be pulled up by only one resistor per signal. pull-up resistor is installed on one board only. (board selection is application specific.) 2. all devices with chipid 1 00 require individual pull-up resistors at ir100cfsbp. lxt98xx chip id 01 lxt98xx chip id 10 +3.3v 215 ? 1% 330 ? ir10ena\ ir10dat ir10cfs\ ir10col\ holdcol ir10clk ? 245 ir10datbp ir10enabp\ dir ena ir10clkbp ab lxt98xx chip id 00 ir10colbp\ ir10cfsbp\ ir10den\ isolate 330 ? 1% 330 ? 1% +3.3v 330 ? ir10den\ ir10clk ir10ena\ ir10dat ir10colbp\ ir10cfsbp\ ir10colbp\ ir10cfsbp\ +3.3v 330 ? 330 ? 330 ? 330 ? stack or segment connector 2 1 comp_sel 1. in stacked configurations, all devices with chipid = 00 are tied together at ir100cfsbp. the entire stack must be pulled up by only one resistor per signal. pull-up resistor is installed on one board only. (board selection is application specific. 2. all devices with chipid 1 00 require individual pull-up resistors at ir100cfsbp.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 75 5.0 test specifications note: table 27 through table 44 and figure 32 through figure 41 represent the target specifications of the lxt98x0 and are subject to change. final values will be guaranteed by test except, where noted, by design. the minimum and maximum values listed in table 29 through table 44 will be guaranteed over the recommended operating conditions specified in table 28 . table 27. absolute maximum ratings parameter symbol min max units supply voltage v cc -0.3 4.0 v storage temperature t st -65 +150 o c caution: exceeding these values may cause permanent damage. functional operation under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 28. operating conditions parameter sym min typ 1 max units recommended supply voltage v cc 3.15 3.3 3.45 v v ccr 3.15 3.3 3.45 v v cct 3.15 3.3 3.45 v recommended operating temperature commercial temperature range ambient t opa 0 ? 70 c case t opc 0 ? 115 c extended temperature range ambient t opa -40 ? +85 c case t opc -18 ? +120 c power consumption 8 ports active p c ?? 3.03 w 6 ports active p c ?? 2.50 w 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. table 29. input system clock 1 requirements parameter 2 sym min typ 3 max units test conditions frequency ?? 25 ? mhz ? frequency tolerance ??? 100 ppm ? duty cycle ? 40 ? 60 % ? 1. the system clock is clk25 (pin 54). 2. these requirements apply to the external clock supplied to the lxt98x0, not to lxt98x0 test specifications. 3. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 76 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 30. i/o electrical characteristics parameter sym min typ 1 max units test conditions input low voltage v il ?? 0.8 v ttl inputs ?? 30 % v cc cmos inputs 2 ?? 1.0 schmitt triggers 3 input high voltage v ih 2.0 ?? v ttl inputs 70 ?? % v cc cmos inputs 2 v cc - 1.0 ?? v schmitt triggers 3 hysteresis voltage ? 1.0 ?? v schmitt triggers 3 output low voltage v ol ?? 0.4 v i ol = 1.6 ma output low voltage (led) v oll ?? 1.0 v i oll = 10 ma output high voltage v oh 2.2 ?? vi oh = 40 a input low current i il -100 ?? a ? input high current i ih ?? 100 a ? output rise / fall time t rf ? 310 nsc l = 15 pf 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. does not apply to irb pins. refer to table 31 and table 32 for irb i/o characteristics. 3. applies to reset, clk25, ir100sngl , ir100col , ir100dat n, ir100clk, and ir10clk pins. table 31. 100 mbps irb electrical characteristics parameter sym min typ 1 max units test conditions output low voltage v ol ? .3 .7 v r l = 330 ? output rise or fall time t rf ? 410 nsc l = 1 5 pf input high voltage v ih v cc - 2.0 ?? v cmos inputs v cc - 1.0 ?? v ir100clk (schmitt trigger) input low voltage v il ?? 2.0 v cmos inputs ?? 1.0 ir100clk (schmitt trigger) hysteresis voltage ? 1.0 ?? v ir100clk (schmitt trigger) 3.3v operation ir100cfs current single drive ?? 6.8 ? ma r l = 215 ? collision ?? 13.5 ? ma r l = 215 ? ir100cfsbp current single drive ?? 16.1 ? ma r l = 91 ? 2 collision ?? 31.8 ? ma r l = 91 ? 2 ir100cfs/bp voltage single drive ?? 1.83 ? v ? collision ?? 0.4 ? v ? 5.0v operation 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. 91 ? resistors provide greater noise immunity. systems using 91 ? resistors are backwards stackable with systems using 100 ? resistors.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 77 ir100cfs current single drive ?? n/a ? ma r l = 215 ? collision ?? n/a ? ma r l = 215 ? ir100cfsbp current single drive ?? 24.2 ? ma r l = 91 ? 2 collision ?? 42 ? ma r l = 91 ? 2 ir100cfs/bp voltage single drive ?? 2.8 ? v ? collision ?? 0.6 ? v ? table 32. 10 mbps irb electrical characteristics parameter sym min typ 1 max units test conditions output low voltage v ol 0.1.4vr l = 330 ? output rise or fall time t rf ? 410 nsc l = 15 pf input high voltage v ih v cc - 2.0 ?? v cmos inputs v cc - 2.0 ?? v ir10clk (schmitt trigger) input low voltage v il ?? 2.0 v cmos inputs ?? 1.0 v ir10clk (schmitt trigger) hysteresis voltage ? 0.5 ?? v ir10clk (schmitt trigger) 3.3v operation ir10cfs current single drive ?? 6.8 ? ma r l = 215 ? collision ?? 13.5 ? ma r l = 215 ? ir10cfsbp current single drive ?? 4.5 ? ma r l = 330 ? collision ?? 8.8 ? ma r l = 330 ? ir10cfs/bp voltage single drive ? 1.3 1.83 2.4 v ? collision ? 0.2 0.4 0.6 v ? 5.0v operation ir10cfs current single drive ?? n/a ? ma r l = 215 ? collision ?? n/a ? ma r l = 215 ? ir10cfsbp current single drive ?? 7.0 ? ma r l = 330 ? collision ?? 13.5 ? ma r l = 330 ? ir10cfs/bp voltage single drive ? 1.9 2.8 3.2 v ? collision ? 0.4 0.6 0.8 v ? 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. table 31. 100 mbps irb electrical characteristics (continued) parameter sym min typ 1 max units test conditions 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. 91 ? resistors provide greater noise immunity. systems using 91 ? resistors are backwards stackable with systems using 100 ? resistors.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 78 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 33. 100base-tx transceiver electrical characteristics parameter sym min typ 1 max units test conditions peak differential output voltage (single ended) v p 0.95 1.0 1.05 v note 2 signal amplitude symmetry ? 98 ? 102 % note 2 signal rise/fall time trf 3.0 ? 5.0 ns note 2 rise/fall time symmetry trfs ?? 0.5 ns note 2 duty cycle distortion ??? +/- 0.5 ns offset from 8 ns pulse width at 50% of pulse peak, overshoot vo ?? 5% ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. measured at line side of transformer, line replaced by 100 ? (1%) resistor. table 34. 10base-t transceiver electrical characteristics parameter sym min typ 1 max units test conditions transmitter peak differential output voltage v p 2.2 2.5 2.8 v measured at line side of transformer, line replaced by 100 ? ( .1%) resistor transmit timing jitter addition 2 ? 8 ? 24 ms 0 line length for internal mau transmit timing jitter added by the mau and pls sections 2, 3 ? 0 ? 11 ns after line model specified by ieee 802.3 for 10base-t internal mau receiver receive input impedance z in ? 20 ? k ? between tpip/tpin differential squelch threshold v ds ? 390 ? mv 5 mhz square wave input, 750 mvpp 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. parameter is guaranteed by design; not subject to production testing. 3. ieee 802.3 specifies maximum jitter additions at 1.5 ns for the aui cable, 0.5 ns from the encoder, and 3.5 ns from the mau.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 79 figure 32. 100 mbps tp port-to-port delay timing table 35. 100 mbps tp port-to-port delay timing parameters parameter sym min typ 1 max units 2 test conditions tpip/n to tpop/n, start of transmission t 1a ?? 46 bt ? tpip/n to tpop/n, end of transmission t 1b ?? 46 bt ? tpip/n collision to tpop/n, start of jam t 1c ?? 46 bt ? tpip/n idle to tpop/n, end of jam t 1d ?? 46 bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. tp input #2 t 1c p input #1 tp output jam t 1d t 1a tp input tp output t 1b normal propagation collision jamming
lxt9860/9880 ? advanced 10/100 repeater with integrated management 80 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 figure 33. 100base-tx mii-to-tp port timing table 36. 100base-tx mii-to-tp port timing parameters parameter sym min typ 1 max units 2 test condition txd, tx_en, tx_er setup to tx_clk high t 2a 10 ?? ns ? txd, tx_en, tx_er hold from tx_clk high t 2b 5 ?? ns ? tx_en sampled to crs asserted t 2c 0 ? 4bt ? tx_en sampled to crs de- asserted t 2d 0 ? 16 bt ? tx_en sampled to tpop/n active (tx latency) t 2e ?? 46 bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. tx_clk txd, tx_en, tx_er crs tpop/n t 2a t 2b t 2c t 2d t 2e
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 81 figure 34. 100base-tx tp-to-mii timing table 37. 100base-tx tp-to-mii timing parameters parameter sym min typ 1 max units 2 test conditions tpip/n in to crs asserted t 3a ?? 46 bt ? tpip/n quiet to crs de-asserted t 3b ?? 46 bt ? crs asserted to rxd, rx_dv, rx_er t 3c 1 ? 4bt ? crs de-asserted to rxd, rx_dv, rx_er de-asserted t 3d ?? 3bt ? rx_clk falling edge to rxd, rx_dv, rx_er valid t 3e ?? 10 ns ? tpip/n in to col asserted t 3f ?? 46 bt ? tpip/n quiet to col de-asserted t 3g ?? 46 bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. rx_clk rxd, rx_dv, rx_er crs tpip/n col t 3a t 3b t 3c t 3d t 3f t 3g t 3e
lxt9860/9880 ? advanced 10/100 repeater with integrated management 82 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 figure 35. 10base-t mii-to-tp timing table 38. 10base-t mii-to-tp timing parameters parameter sym min typ 1 max units 2 test conditions txd, tx_en, tx_er setup to tx_clk high t 10a 10 ?? ns ? txd, tx_en, tx_er hold from tx_clk high t 10b 5 ?? ns ? tx_en sampled to crs asserted t 10c 0 .9 2 bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 10base-t = 10 -7 s or 100 ns. tx_clk txd, tx_en, tx_er crs t 10a t 10b t 10c
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 83 figure 36. 10base-t tp-to-mii timing table 39. 10base-t tp-to-mii timing parameters parameter sym min typ 1 max units 2 test conditions tpip/n in to crs asserted t 11a 5 6.6 8 bt ? crs asserted to rxd, rx_dv, rx_er t 11b 70 76 84 bt ? rx_clk falling edge to rxd, rx_dv, rx_er valid t 11c ?? 10 ns ? tpip/n in to col asserted t 11d 6 7.4 9 bt ? 1. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 10base-t = 10 -7 s or 100 ns. rx_clk rxd, rx_dv, rx_er crs tpip/n col t 11a t 11b t 11c t 11d
lxt9860/9880 ? advanced 10/100 repeater with integrated management 84 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 figure 37. 100 mbps tp-to-irb timing table 40. 100 mbps tp-to-irb timing parameters 1 parameter sym min typ 2 max units 3 test conditions tpip/n to ir100dv low t 12a 17 24 30 bt ? ir100dat to ir100clk setup time. t 12b ? 4 ? ns ? ir100dat to ir100clk hold time. t 12c ? 0 ? ns ? 1. this table contains propagation delays from the tp ports to the irb for normal repeater operation. all values in this table are output timings. 2. typical figures are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 3. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 100base-t = 10 -8 s or 10 ns. figure 38. 10 mbps tp-to-irb timing tpip/n ir100dv ir100cfs 1r100col ir100dat<4:0> t 12a t 12b ir100clk t 12c tpip/n ir10ena ir10dat t 13a t 13b ir10clk t 13c see table 41 , note 3
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 85 table 41. 10 mbps tp-to-irb timing parameters 1 parameter 2 sym min typ 3 max units 4 test conditions tpip/n to ir10ena low t 13a 3 5.1 7 bt ? ir10clk rising edge to ir10dat rising edge. t 13b 25 - 55 ns 330 ? pull-up, 150 pf load on ir10dat. 1 k ? pull-up, 150 pf load on irclk. ir10clk rising edge to ir10dat falling edge. t 13c 5 - 25 ns 1. this table contains propagation delays from the tp ports to the irb for normal repeater operation. all values in this table are output timings. 2. there is a delay of approximately 13 to 16 bit times between the assertion of ir10ena and the assertion of ir10clk and ir10dat. this delay does not affect repeater operation because downstream devices begin generating preamble as soon as ir10ena is asserted. 3. typical values are at 25 c and are for design aid only; not guaranteed and not subject to production testing. 4. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 10base-t = 10 -7 s or 100 ns. figure 39. 10 mbps irb-to-tp port timing macactive ir10ena ir10dat t 14a t 14b ir10clk t 14c tpop/n t 14d
lxt9860/9880 ? advanced 10/100 repeater with integrated management 86 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 42. 10 mbps irb-to-tp port timing parameters parameter sym min typ 1 max units 2 test conditions macactive to ir10ena assertion delay 3 t 14a ? 100 ? ns macactive high to ir10ena low. 4 ir10dat (input) to ir10clk setup time t 14b ? 20 ? ns ir10dat valid to ir10clk rising edge. 4 ir10clk to ir10dat (input) hold time t 14c ? 0 ? ns ir10clk rising edge to ir10dat change. 4 ir10ena asserted to tpop/n active t 14d 4 5.1 6 bt ? 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. bit time (bt) is the duration of one bit as transferred to/from the mac and is the reciprocal of bit rate. bt for 10base-t = 10 -7 s or 100 ns. 3. external devices should allow at least one 10 mhz clock cycle (10 ns) between assertion of macactive and ir10ena. 4. input. figure 40. serial management interface timing table 43. serial management interface timing characteristics parameter sym min typ 1 max units test conditions serclk input frequency ??? 2.0 mhz depending on reconfig, this is either an input or output. serclk output frequency ? 625 ? khz data to clock setup time t15a 0 ?? ns srx valid to serclk rising edge. 2 clock to data hold time t15b 200 ?? ns serclk rising edge to srx change. 2 data propagation delay t15c ?? 200 ns serclk falling edge to stx valid. 3 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. 2. input. 3. output. t15a t15b t15c serclk srx stx
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 87 6.0 register definitions 6.1 register map the lxt98x0 register set is composed of multiple 32-bit registers as mapped in table 45 . all register addresses are hexadecimal. figure 41. prom interface timing table 44. prom interface timing characteristics parameter sym min typ 1 max units test conditions prom_clk ?? 1.0 mhz prom_clk frequency. clk to prom_cs delay t16a ? 200 ns clk falling edge to prom_cs. clk to prom_dtout delay t16b ? 20 ns clk falling edge to prom_dtout. prom_dtin to clk setup time t16c 20 ? ns prom_dtin to clk rising edge. prom_dtin to clk hold time t16d 20 ? ns prom_dtin to clk rising edge. 1. typical values are at 25 c and are for design aid only; they are not guaranteed and not subject to production testing. prom_dtout prom_cs prom_clk t 16a t 16b prom_dtin t 16c t 16d
lxt9860/9880 ? advanced 10/100 repeater with integrated management 88 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 45. register map class register size (bits) access 1 offset (hex) page ref. port counters : tp and mii ports formula: ((n-1)*16) + offset n = port number. 0 < n < 11 rptrmonitorportreadableframes 32 r/w 0 95 rptrmonitorportreadableoctets(lower/upper) 64 r/w 1,2 95 rptrmonitorportframechecksequence 32 r/w 3 95 rptrmonitorportalignmenterrors 32 r/w 4 95 rptrmonitorportframestoolong 32 r/w 5 95 rptrmonitorportshortevents 32 r/w 6 95 rptrmonitorportrunts 32 r/w 7 95 rptrmonitorportcollisions 32 r/w 8 95 rptrmonitorportlateevents 32 r/w 9 95 rptrmonitorportverylongevents 32 r/w a 95 rptrmonitorportdataratemismatches 32 r/w b 95 rptrmonitorportautopartitions 32 r/w c 95 rptrtracksourceaddrchanges 32 r/w d 95 rptrmonitorportbroadcastpkts 32 r/w e 95 rptrmonitorportmulticastpkts 32 r/w f 95 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. if register clear bit is set to ? 1 ? , then clearing of the associated bit is done by writing ? 1 ? to it, otherwise this register self clears upon read. register clear (bit 11) is set through the repeater configuration register. (refer to table 75 on page 109 .)
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 89 additional counters: (100 only) rptrmonitorportisolates - port 1 32 r/w a0 95 rptrmonitorportisolates - port 2 32 r/w a1 95 rptrmonitorportisolates - port 3 32 r/w a2 95 rptrmonitorportisolates - port 4 32 r/w a3 95 rptrmonitorportisolates - port 5 32 r/w a4 95 rptrmonitorportisolates - port 6 32 r/w a5 95 rptrmonitorportisolates - port 7 32 r/w a6 95 rptrmonitorportisolates - port 8 32 r/w a7 95 rptrmonitorportisolates-mii port 1 32 r/w a8 95 rptrmonitorportisolates-mii port 2 32 r/w a9 95 rptrmonitorsymbolerrorduringpacket - port 1 32 r/w aa 96 rptrmonitorsymbolerrorduringpacket - port 2 32 r/w ab 96 rptrmonitorsymbolerrorduringpacket - port 3 32 r/w ac 96 rptrmonitorsymbolerrorduringpacket - port 4 32 r/w ad 96 rptrmonitorsymbolerrorduringpacket - port 5 32 r/w ae 96 rptrmonitorsymbolerrorduringpacket - port 6 32 r/w af 96 rptrmonitorsymbolerrorduringpacket - port 7 32 r/w b0 96 rptrmonitorsymbolerrorduringpacket - port 8 32 r/w b1 96 reserved 32 r/w b2 96 reserved 32 r/w b3 96 table 45. register map (continued) class register size (bits) access 1 offset (hex) page ref. 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. if register clear bit is set to ? 1 ? , then clearing of the associated bit is done by writing ? 1 ? to it, otherwise this register self clears upon read. register clear (bit 11) is set through the repeater configuration register. (refer to table 75 on page 109 .)
lxt9860/9880 ? advanced 10/100 repeater with integrated management 90 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 rmon counters: (10 only) etherstatsoctets 32 r/w b4 97 etherstatspkts 32 r/w b5 97 etherstatsbroadcastpkts 32 r/w b6 97 etherstatsmulticastpkts 32 r/w b7 97 etherstatscrcalignerrors 32 r/w b8 97 etherstatsundersizepkts 32 r/w b9 97 etherstatsoversizepkts 32 r/w ba 97 etherstatsfragments 32 r/w bb 97 etherstatsjabbers 32 r/w bc 97 etherstatscollisions/ rptrmonitortransmitcollisions 32 r/w bd 97 etherstatspkts64octets 32 r/w be 97 etherstatspkts65to127octets 32 r/w bf 97 etherstatspkts128to255octets 32 r/w c0 97 etherstatspkts256to511octets 32 r/w c1 97 etherstatspkts512to1023octets 32 r/w c2 97 etherstatspkts1024to1518octets 32 r/w c3 97 reserved 32 r/w c4 97 rptrmonitortotaloctets(lower/upper) 32 r/w c5 97 table 45. register map (continued) class register size (bits) access 1 offset (hex) page ref. 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. if register clear bit is set to ? 1 ? , then clearing of the associated bit is done by writing ? 1 ? to it, otherwise this register self clears upon read. register clear (bit 11) is set through the repeater configuration register. (refer to table 75 on page 109 .)
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 91 rmon counters: (100 only) etherstatsoctets(lower/upper) 64 r/w c6, c7 98 etherstatspkts 32 r/w c8 98 etherstatsbroadcastpkts 32 r/w c9 98 etherstatsmulticastpkts 32 r/w ca 98 etherstatscrcalignerrors 32 r/w cb 98 etherstatsundersizepkts 32 r/w cc 98 etherstatsoversizepkts 32 r/w cd 98 etherstatsfragments 32 r/w ce 98 etherstatsjabbers 32 r/w cf 98 etherstatscollisions/ rptrmonitortransmitcollisions 32 r/w d0 98 etherstatspkts64octets 32 r/w d1 98 etherstatspkts65to127octets 32 r/w d2 98 etherstatspkts128to255octets 32 r/w d3 98 etherstatspkts256to511octets 32 r/w d4 98 etherstatspkts512to1023octets 32 r/w d5 98 etherstatspkts1024to1518octets 32 r/w d6 98 reserved 32 r d7 98 rptrmonitortotaloctets(lower/upper) 64 r/w d8, d9 98 port addresses rptraddrtracknewlastsrcaddress - port 1 48 r/w da, db 99 rptraddrtracknewlastsrcaddress - port 2 48 r/w dc, dd 99 rptraddrtracknewlastsrcaddress - port 3 48 r/w de, df 99 rptraddrtracknewlastsrcaddress - port 4 48 r/w e0, e1 99 rptraddrtracknewlastsrcaddress - port 5 48 r/w e2, e3 99 rptraddrtracknewlastsrcaddress - port 6 48 r/w e4, e5 99 rptraddrtracknewlastsrcaddress - port 7 48 r/w e6, e7 99 rptraddrtracknewlastsrcaddress - port 8 48 r/w e8, e9 99 table 45. register map (continued) class register size (bits) access 1 offset (hex) page ref. 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. if register clear bit is set to ? 1 ? , then clearing of the associated bit is done by writing ? 1 ? to it, otherwise this register self clears upon read. register clear (bit 11) is set through the repeater configuration register. (refer to table 75 on page 109 .)
lxt9860/9880 ? advanced 10/100 repeater with integrated management 92 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 authorized addresses authorized sa port 1 48 r/w ee, ef 99 authorized sa port 2 48 r/w f0, f1 99 authorized sa port 3 48 r/w f2, f3 99 authorized sa port 4 48 r/w f4, f5 99 authorized sa port 5 48 r/w f6, f7 99 authorized sa port 6 48 r/w f8, f9 99 authorized sa port 7 48 r/w fa, fb 99 authorized sa port 8 48 r/w fc, fd 99 search addresses (10 or 100) search address 48 r/w 102, 103 100 search match address 10 r(/w) 2 104 100 repeater port control port link control enable 8 r/w 105 102 port alternate partition algorithm control 10 r/w 108 101 port enable 10 r/w 109 101 port learn enable 20 r/w 10a 102 reserved r/w 10b 102 repeater port status port link status 8 r 10c 103 port polarity status 8 r 10d 103 port partition status 10 r 10e 103 port speed status 10 r 110 103 port isolation status (tx) 10 r 111 103 table 45. register map (continued) class register size (bits) access 1 offset (hex) page ref. 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. if register clear bit is set to ? 1 ? , then clearing of the associated bit is done by writing ? 1 ? to it, otherwise this register self clears upon read. register clear (bit 11) is set through the repeater configuration register. (refer to table 75 on page 109 .)
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 93 phy port status auto negotiate link partner advertisement (port 1) 16 r 112 104 auto negotiate link partner advertisement (port 2) 16 r 113 104 auto negotiate link partner advertisement (port 3) 16 r 114 104 auto negotiate link partner advertisement (port 4) 16 r 115 104 auto negotiate link partner advertisement (port 5) 16 r 116 104 auto negotiate link partner advertisement (port 6) 16 r 117 104 auto negotiate link partner advertisement (port 7) 16 r 118 104 auto negotiate link partner advertisement (port 8) 16 r 119 104 auto negotiate expansion (port 1) 16 r 11a 105 auto negotiate expansion (port 2) 16 r 11b 105 auto negotiate expansion (port 3) 16 r 11c 105 auto negotiate expansion (port 4) 16 r 11d 105 auto negotiate expansion (port 5) 16 r 11e 105 auto negotiate expansion (port 6) 16 r 11f 105 auto negotiate expansion (port 7) 16 r 120 105 auto negotiate expansion (port 8) 16 r 121 105 phy port status register (port 1) 16 r/w 122 105 phy port status register (port 2) 16 r/w 123 105 phy port status register (port 3) 16 r/w 124 105 phy port status register (port 4) 16 r/w 125 105 phy port status register (port 5) 16 r/w 126 105 phy port status register (port 6) 16 r/w 127 105 phy port status register (port 7) 16 r/w 128 105 phy port status register (port 8) 16 r/w 129 105 table 45. register map (continued) class register size (bits) access 1 offset (hex) page ref. 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. if register clear bit is set to ? 1 ? , then clearing of the associated bit is done by writing ? 1 ? to it, otherwise this register self clears upon read. register clear (bit 11) is set through the repeater configuration register. (refer to table 75 on page 109 .)
lxt9860/9880 ? advanced 10/100 repeater with integrated management 94 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 phy port control auto negotiate advertise (ports 1) 16 r/w 12a 107 auto negotiate advertise (ports 2) 16 r/w 12b 107 auto negotiate advertise (ports 3) 16 r/w 12c 107 auto negotiate advertise (ports 4) 16 r/w 12d 107 auto negotiate advertise (ports 5) 16 r/w 12e 107 auto negotiate advertise (ports 6) 16 r/w 12f 107 auto negotiate advertise (ports 7) 16 r/w 130 107 auto negotiate advertise (ports 8) 16 r/w 131 107 phy port control register (port 1) 16 r/w 132 107 phy port control register (port 2) 16 r/w 133 107 phy port control register (port 3) 16 r/w 134 107 phy port control register (port 4) 16 r/w 135 107 phy port control register (port 5) 16 r/w 136 107 phy port control register (port 6) 16 r/w 137 107 phy port control register (port 7) 16 r/w 138 107 phy port control register (port 8) 16 r/w 139 107 repeater port control/ status repeater configuration 32 r/w 13a 108 repeater serial configuration 8 r 13b 108 device/rev id 32 r 13c 108 reserved 32 r 13d 108 reserved 32 r 13e 108 reserved 32 r 13f 108 global led control register 6 r/w 140 108 port led control register 20 r/w 141 108 led timer control register 16 r/w 142 108 mii status 2 r 143 103 repeater reset 1 w 144 108 software reset 1 w 145 109 interrupt status 16 r(/w) 2 146 113 interrupt mask 16 r/w 147 113 serial controller assign address 32 w 188, 189 108 prom address 32 r 190, 191 108 table 45. register map (continued) class register size (bits) access 1 offset (hex) page ref. 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. if register clear bit is set to ? 1 ? , then clearing of the associated bit is done by writing ? 1 ? to it, otherwise this register self clears upon read. register clear (bit 11) is set through the repeater configuration register. (refer to table 75 on page 109 .)
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 95 6.2 counter registers all counters power up to zero. when reading a 64-bit counter, read the lower address (lower 32 bits of counter) first, followed by the upper address. the first read causes all 64 bits to be simultaneously latched into an internal holding register. the second read is directed to this holding register. the statistics bit must be set off to write to the counters. a write operation of the counters is non-atomic for the 64 bit counters. for further definitions refer to rfc 1757 and clause 30 of ieee 802.3. the readableframe counter max size threshold can either be 1518 or 1522. all counters expecting a maximum transmission unit (mtu) size of 1518 can be changed to a new value of 1522 by setting the extended frame bit (13) in the repeater configuration register. 6.2.1 port counter registers the port counter descriptions in table 46 are intended to be illustrative. for the exact definition of these counters, refer to the repeater mib, rfc 1516. all counters count packets, octets or events that were received at each port. in the descriptions, the length of a packet never includes preamble or framing bits (start of frame, end of frame, dribble bits, etc.), but an ? event ? does include these items. all port counters are read-only. table 46. port counter registers name offset addr 1,2 description rptrmonitorportreadableframes 0x0 counts valid-length (64 to 1518 bytes), valid-crc, collision-free packets. depending on the state of the unicastframecount bit (6) in the repeater configuration register, this counter counts either all packets (unicastframecount = 0) or only unicast packets (unicastframecount = 1). see note 3. rptrmonitorportreadableoctets (lower/upper) 0x1, 0x2 counts the number of octets in all valid-length (64 to 1518 bytes), valid-crc, collision-free packets, not including preamble and framing bits. this register is not affected by the unicastframecount bit. see note 3. rptrmonitorportframechecksequence 0x3 counts valid length, collision-free packets that had fcs errors, but were correctly framed (had an integral number of octets). if a framing error occurs, this counter does not increment. rptrmonitorportalignmenterrors 0x4 counts valid length, collision-free packets that had fcs errors and were incorrectly framed (had a non-integral number of octets). 1. all offset addresses are expressed in hex. 2. replace ? x ? in address with specific port to be addressed (offsets 0 through 9 correspond to ports 1 through 10). 3. the readableframe counter max size threshold can either be 1518 or 1522. all counters expecting a mtu size of 1518 can be changed to a new value of 1522 by setting the extended frame bit (13) in the repeater configuration register. 4. for 100 mbps: the ? short events ? register counts events < 88 bit times; the ? port runts ? register counts events > 92. a 4-bit-time differential exists because 100 mbps operates with nibble boundaries, so data packets < 4 bits are counted as 4. 5. a0 - a7 corresponds to port 1 - port 8. 6. aa - b1 corresponds to port 1 - port 8.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 96 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 6.2.2 rmon counter registers the interface counter descriptions in table 47 are intended to be illustrative. for the exact definition of these counters, refer to the rmon mib, rfc 1757. all counters count events, octets or packets that were received from the interface. packet length never includes preamble or framing bits (start of frame, end of frame, dribble bits, etc.). rptrmonitorportframestoolong 0x5 counts packets that had a length greater than 1518 octets. rptrmonitorportshortevents 0x6 counts events < ? shorteventmax ? . 10 mbps: 74-82 bit times. 100 mbps: 74-84 bit times. see note 4. rptrmonitorportrunts 0x7 counts events > ? shorteventmax ? , but <512 bits. see note 4. rptrmonitorportcollisions 0x8 counts the number of collisions that occurred, not including late collisions. rptrmonitorportlateevents 0x9 counts the number of times a collision is detected after the ? lateeventthreshold ? time (480-565 bits). this event is counted here and also in the ? collisions ? attribute. rptrmonitorportverylongevents 0xa counts the number of times the transmitter is active for greater than the mjlp time. rptrmonitorportdataratemismatches 0xb counts the number of times the frequency or data rate of the incoming signal is detectably different from that of the local transmit frequency. rptrmonitorportautopartitions 0xc counts the number of times this port has been partitioned from the network. rptrtracksourceaddrchanges 0xd counts the number of times the source address has changed. rptrmonitorportbroadcastpkts 0xe counts the number of good broadcast packets received by this port. rptrmonitorportmulticastpkts 0xf counts the number of good multicast packets received by this port. rptrmonitorportisolates 0a0 ? 0a7 5 counts the number of times a port auto isolates. note: when these counters increment, none of the other port counters increment, since the frame never had a valid start. rptrmonitorsymbolerrorduringpacket 0aa-0b1 6 counts the number of time a packet contained symbol errors. only one symbol error is counted per packet. on the mii ports this counter is invalid. table 46. port counter registers (continued) name offset addr 1,2 description 1. all offset addresses are expressed in hex. 2. replace ? x ? in address with specific port to be addressed (offsets 0 through 9 correspond to ports 1 through 10). 3. the readableframe counter max size threshold can either be 1518 or 1522. all counters expecting a mtu size of 1518 can be changed to a new value of 1522 by setting the extended frame bit (13) in the repeater configuration register. 4. for 100 mbps: the ? short events ? register counts events < 88 bit times; the ? port runts ? register counts events > 92. a 4-bit-time differential exists because 100 mbps operates with nibble boundaries, so data packets < 4 bits are counted as 4. 5. a0 - a7 corresponds to port 1 - port 8. 6. aa - b1 corresponds to port 1 - port 8.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 97 table 47. rmon counter registers - 10 mbps name addr description etherstatsoctets 0b4 counts total umber of data octets including those in bad packets and octets in fcs fields, but does not include preamble or other framing bits. etherstatspkts 0b5 total number of packets received from network, including errored packets. etherstatsbroadcastpkts 0b6 total number of good broadcast packets received. etherstatsmulticastpkts 0b7 total number of good multicast packets received. this number does not include broadcast packets. etherstatscrcalignerrors 0b8 total number of valid-length packets (64 to 1518 bytes inclusive) that did not contain an integral number of octets or had a bad frame check sequence (fcs). etherstatsundersizepkts 0b9 total number of well-formed packets that were smaller than 64 octets (excluding framing bits but including fcs octets). etherstatsoversizepkts 0ba total number of well-formed packets that were longer than 1518 octets (excluding framing bits but including fcs octets). etherstatsfragments 0bb total number of packets received that were not an integral number of octets in length or that had a bad frame check sequence (fcs) or frame alignment error(fae), and were less than 64 octets in length (excluding framing bits, but including fcs octets). note: a packet without sfd or 0 length is counted here. etherstatsjabbers 0bc total number of packets received that were longer than 1518 octets (excluding framing bits, but including fcs octets), and were not an integral number of octets in length or had a bad frame check sequence (fcs). etherstatscollisions/ rptrmonitor transmit collisions 0bd the best estimate of the total number of collisions on this segment. etherstatspkts64octets 0be total number of packets (including error packets) received that were 64 octets in length (excluding framing bits but including fcs octets). etherstatspkts65to127octets 0bf total number of packets (including error packets) received that were between 65 and 127 octets in length inclusive (excluding framing bits but including fcs octets). etherstatspkts128to255octets 0c0 total number of packets (including error packets) received that were between 128 and 255 octets in length inclusive (excluding framing bits but including fcs octets). etherstatspkts256to511octets 0c1 total number of packets (including error packets) received that were between 256 and 511 octets in length inclusive (excluding framing bits but including fcs octets). etherstatspkts512to1023octets 0c2 total number of packets (including error packets) received that were between 512 and 1023 octets in length inclusive (excluding framing bits but including fcs octets). etherstatspkts1024to1518octets 0c3 the total number of packets (including error packets) received that were between 1024 and 1518 octets in length inclusive (excluding framing bits but including fcs octets). reserved 0c4 - rptrmonitortotaloctets 0c5 total number of octets contained in valid frames received on this segment.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 98 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 48. rmon counter registers - 100 mbps name addr description etherstatsoctets (lower/upper) 0c6 0c7 counts total umber of data octets including those in bad packets and octets in fcs fields, but does not include preamble or other framing bits. etherstatspkts 0c8 total number of packets received from network, including errored packets. etherstatsbroadcastpkts 0c9 total number of good broadcast packets received. etherstatsmulticastpkts 0ca total number of good multicast packets received. this number does not include broadcast packets. etherstatscrcalignerrors 0cb total number of valid-length packets (64 to 1518 bytes inclusive) that did not contain an integral number of octets or had a bad frame check sequence (fcs). etherstatsundersizepkts 0cc total number of well-formed packets that were smaller than 64 octets (excluding framing bits but including fcs octets). etherstatsoversizepkts 0cd total number of well-formed packets that were longer than 1518 octets (excluding framing bits but including fcs octets). etherstatsfragments 0ce total number of packets received that were not an integral number of octets in length or that had a bad frame check sequence (fcs) or frame alignment error(fae), and were less than 64 octets in length (excluding framing bits, but including fcs octets). note: a packet without sfd or 0 length is counted here. etherstatsjabbers 0cf total number of packets received that were longer than 1518 octets (excluding framing bits, but including fcs octets), and were not an integral number of octets in length or had a bad frame check sequence (fcs). etherstatscollisions/ rptrmonitor transmit collisions 0d0 the best estimate of the total number of collisions on this segment. etherstatspkts64octets 0d1 total number of packets (including error packets) received that were 64 octets in length (excluding framing bits but including fcs octets). etherstatspkts65to127octets 0d2 total number of packets (including error packets) received that were between 65 and 127 octets in length inclusive (excluding framing bits but including fcs octets). etherstatspkts128to255octets 0d3 total number of packets (including error packets) received that were between 128 and 255 octets in length inclusive (excluding framing bits but including fcs octets). etherstatspkts256to511octets 0d4 total number of packets (including error packets) received that were between 256 and 511 octets in length inclusive (excluding framing bits but including fcs octets). etherstatspkts512to1023octets 0d5 total number of packets (including error packets) received that were between 512 and 1023 octets in length inclusive (excluding framing bits but including fcs octets). etherstatspkts1024to1518octets 0d6 the total number of packets (including error packets) received that were between 1024 and 1518 octets in length inclusive (excluding framing bits but including fcs octets). reserved od7 - rptrmonitortotaloctets (lower/upper) 0d8, 0d9 total number of octets contained in valid frames received on this segment.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 99 6.3 ethernet address registers all ethernet address registers consist of two 32-bit registers that together contain a 48-bit ethernet address. address values are unknown on power up. 6.3.1 port address registers the port address register set is described in table 50 . the tracking registers continuously monitor the source addresses of packets emanating from the corresponding ports. the authorized address registers can be used for security functions. 6.3.2 search address registers the lxt98x0 offers an on-board address search mechanism. should the user wish to find out if a particular source address has been seen on any of the ports, on any of the segments, this register would be used. each port within a lxt98x0 chip is checked for traffic originating from the source address matching the search address register. if a match is found, the port number where the traffic originated is saved, thus allowing software to determine where the address is located. the search address match register contains the port from the search address match function. table 49. ethernet address register bit assignments upper address bits 31:16 reserved. bits 15:0 contain bits 47:32 of the ethernet address. lower address bits 31:0 contain bits 31:0 of the ethernet address. table 50. port address tracking registers name type 1 port addr 2 description rptraddrtracknewlastsrcaddress rw 1 2 3 4 5 6 7 8 9 10 0da, 0db 0dc, 0dd 0de, 0df 0e0, 0e1 0e2, 0e3 0e4, 0e5 0e6, 0e7 0e8, 0e9 0ea, 0eb 0ec, 0ed stores the value of the last source address received. attribute is 6 bytes long. can also act as newlastsourceaddress via sw. these addresses power up unknown, but can be zeroed by software. example address: 00-20-7b-03-02-01 first read: msb 037b2000 lsb . second read: msb xxxx0102 lsb all addresses or address pairs must read in order. only the first read updates the holding register. x ? s are currently defined as zeros. authorizedsourceaddress r/w 1 2 3 4 5 6 7 8 0ee, 0ef 0f0, 0f1 0f2, 0f3 0f4, 0f5 0f6, 0f7 0f8, 0f9 0fa, 0fb 0fc, 0fd used for security address comparisons. an auto learn mode is available. typically, this address matches: rptraddrtracknewlastsrcaddress register. these addresses power up unknown, but can be zeroed by software. 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. all offset addresses are expressed in hex.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 100 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 the search address and search address match registers are described in table 51 ; bit assignments are provided in table 53 ; search address match bit definitions are given in table 54 . table 51. search address/search address match register name type addr description search address r/w 102, 103 this register reflects search address search match address 104 this register reflects search address match status table 52. search address register bit assignments upper address bits 31:16 reserved. bits 15:0 contain bits 47:32 of the address. lower address bits 31:0 contain bits 31:0 of the address. table 53. search match address bit assignments 31:109876543210 rsvd port 10 (mii 2) port 9 (mii 1) port 8 port 7 port 6 port 5 port 4 port 3 port 2 port 1 table 54. search match address bit definitions name type 1 description default reserved r - 0 port 10 (mii 2) r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 9 (mii 1) r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 8 r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 7 r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 6 r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 5 r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 4 r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 3 r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 2 r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0 port 1 r/w 1 = address in search address register matched on this port. 0 = address did not match search address on this port. 0
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 101 6.4 repeater port control registers the control register set includes general port control as well as link and learn enable registers. 6.4.1 general port control registers the general port control register bit assignments are described in table 55 . refer to table 56 for the general port control register descriptions. 6.4.2 port link control register the port link control register bit assignments are described in table 57 . refer to table 58 for the port link control register description. table 55. port control register bit assignments 31:10 9 8 7 6 5 4 3 2 1 0 rsvd port 10 (mii 2) port 9 (mii 1) port 8port 7port 6port 5port 4port 3port 2port 1 1. bits 8 and 9 (mii ports) are not used by the link control register. table 56. general port control registers name type 1 addr description default port alternate partition algorithm control (100 mbps only) r/w 108 un-partition. the lxt98x0 twisted-pair ports support two un-partition algorithms: the alternative un-partition algorithm, which complies with ieee specification 802.3aa, un-partitions a port on either transmit or receive of at least 450-560 bits without collision. 2 the normal algorithm, which complies with the ieee specification 802.3u, is available through the management interface. this algorithm un-partitions a port only when data is transmitted to the port for 450-560 bit times without a collision. provides per-port selection of partition algorithms. 0 = normal 1 = alternate 1 port enable r/w 109 this register controls whether a port is enabled/disabled. if the mgr_pres signal is low on power up, then all ports are disabled until such time that management software re-enables them. otherwise, the ports are enabled at power-up. 0 = disable 1 = enable 1 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. 2. alternate partition mode also causes port to partition after a single long collision. table 57. port link control and status register bit assignments 31:876543210 rsvd port 8port 7port 6port 5port 4port 3port 2port 1
lxt9860/9880 ? advanced 10/100 repeater with integrated management 102 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 6.4.3 port learn enable register the port learn enable register bit assignments are described in table 59 . refer to table 60 for the port learn enable register description. 6.5 repeater port status registers the port status register bit assignments are described in table 61 . refer to table 62 for the port status register descriptions. table 58. port link control register name type 1 addr description default port link control enable r/w 105 this register controls the link function of the twisted-pair ports. 1 = use normal link control. the port only remains connected to the network so long as link pulses or idles are being received. 0 = disable normal link control. the port is no longer disconnected due to link fail. 1 1. r = read only; w = write only; r/w = read/write; lh = latch high; ll = latch low; sc = self clearing. table 59. port learn enable register 31:20191817161514131211109876543210 rsvd port 10 (mii 2) port 9 (mii 1) port 8 port 7 port 6 port 5 port 4 port 3 port 2 port 1 table 60. port learn enable register name type addr description default port learn enable r/w 10a this register sets the level of learning each port uses. the learn settings are as follows: 00 bit 1 bit 0 function 0 0 learn each new source addresses. 01 next lock. learn only the first source address encountered. after a port learns its first address, it changes the authorized learn bits (for that port) to a ? 10 ? to lock down the address. 10 lock. hardware locked-down the address. only software can write to this address. 1 1 reserved.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 103 table 61. port status register bit assignments 31:10 9 8 7 6 5 4 3 2 1 0 rsvd port 10 (mii 2) port 9 (mii 1) port 8port 7port 6port 5port 4port 3port 2port 1 1. not all status registers use bits 8 and 9. table 62. port status registers name description type 1 addr default port link status 2 reflects the current link status of each twisted-pair port. 1 = link up. 0 = link down. r 10c 0 port polarity status 2 reflects the current polarity status of each twisted-pair port. 1 = polarity reversed. 0 = polarity normal. r 10d 0 port partition status reflects the current partition status of each twisted-pair port. 1 = port is partitioned. 0 = port is not partitioned. r 10e 0 port speed status indicates the current speed status of each port. 1 = port is connected at 100 mbps. 0 = port is connected at 10 mbps. r110 0 port isolation status indicates the current isolation status of each twisted-pair port. 1 = port is isolated. 0 = port is not isolated. r 111 0 phy port status (summary) individual per-port status registers. refer to table 68 on page 105 for addressing and other details. r/w - 1. r = read only 2. register does not track mii port status. bits 8 and 9 reserved. table 63. mii speed status bit assignments 31:10 9 8 7 6 5 4 3 2 1 0 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd mii 2 mii 1 table 64. mii status bit definitions name description type 1 addr default miispeed status individual mii port speed status registers. 1 = 100 mbps 0 = 10 mbps r 143 lor 1. r = read only; w = write only, r/w = read/write, lor = latch on reset, ll = latch low, sc = self clearing
lxt9860/9880 ? advanced 10/100 repeater with integrated management 104 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 6.6 phy port status registers the port auto-negotiation registers are described in table 65 through table 71 . table 65. auto-negotiation registers name size bits addr type description auto-negotiate link partner advertisement #1 (port 1) 32 112 r see table 66 on page 104 . auto-negotiate link partner advertisement #1 (port 2) 32 113 r auto-negotiate link partner advertisement #1 (port 3) 32 114 r auto-negotiate link partner advertisement #1 (port 4) 32 115 r auto-negotiate link partner advertisement #1 (port 5) 32 116 r auto-negotiate link partner advertisement #1 (port 6) 32 117 r auto-negotiate link partner advertisement #1 (port 7) 32 118 r auto-negotiate link partner advertisement #1 (port 8) 32 119 r auto-negotiate expansion #1 (port 1) 32 11a r see table 67 on page 105 . auto-negotiate expansion #1 (port 2) 32 11b r auto-negotiate expansion #1 (port 3) 32 11c r auto-negotiate expansion #1 (port 4) 32 11d r auto-negotiate expansion #1 (port 5) 32 11e r auto-negotiate expansion #1 (port 6) 32 11f r auto-negotiate expansion #1 (port 7) 32 120 r auto-negotiate expansion #1 (port 8) 32 121 r table 66. auto-negotiate link partner advertisement bit definitions bit name description type 1 default 31.16 reserved reserved. r 0 15 next page 1 = link partner has ability to send multi pages. 0 = link partner has no ability to send multi pages. r0 14 reserved reserved. r 0 13 remote fault 1 = remote fault. 0 = no remote fault. r0 12:10 reserved reserved. r 0 9 100base-t4 1 = link partner is 100base-t4 compatible. 0 = link partner is not 100base-t4 compatible. r0 8 100base-tx fd 1 = link partner is 100base-tx fd capable. 0 = link partner is not 100base-tx fd capable. r0 7 100base-tx 1 = link partner is 100base-tx capable. 0 = link partner is not 100base-tx capable. r0 1. r = read only; w = write only, r/w = read/write, lh = latch high, ll = latch low, sc = self clearing
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 105 6 10base-t fd 1 = link partner is 10base-t fd capable. 0 = link partner is not 10base-t fd capable. r0 5 10base-t 1 = link partner is 10base-t capable. 0 = link partner is not 10base-t capable. r0 4:0 selector field ieee 802.3 r 00000 table 67. auto-negotiate expansion bit definitions bit name description type 1 default 31.5 reserved reserved. r 0 4 parallel detection fault 1 = more than one of the pmas detects a valid link. 0 = no conflict. r/lh 0 3 link partner next page able 1 = link partner is next page able. 0 = link partner is not next page able. r0 2 next page able 0 = local device is not next page able. r 0 1 page received 1 = 3 identical and consecutive link code words are received. 0 = 3 identical and consecutive link code words have not been received. r/lh 0 0 link partner auto negotiate able 1 = link partner is auto negotiate able. 0 = link partner is not auto negotiate able. r/lh 0 1. r = read only; w = write only, r/w = read/write, lh = latch high, ll = latch low, sc = self clearing table 68. phy port status register summary name size addr type description port 1 32 122 r per port register indicating current status of operating conditions. port 2 32 123 r port 3 32 124 r port 4 32 125 r port 5 32 126 r port 6 32 127 r port 7 32 128 r port 8 32 129 r table 66. auto-negotiate link partner advertisement bit definitions (continued) bit name description type 1 default 1. r = read only; w = write only, r/w = read/write, lh = latch high, ll = latch low, sc = self clearing
lxt9860/9880 ? advanced 10/100 repeater with integrated management 106 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 69. phy port status register bit definitions bit name description r/w default 31:16 reserved reserved. r 0 15 100base-t4 1 = port able to perform 100base-t4. 0 = port not able to perform 100base-t4. r0 14 100base-x full duplex 1 = port able to perform full-duplex 100base-x. 0 = port not able to perform full-duplex 100base-x. r0 13 100base-x half duplex 1 = port able to perform half-duplex 100base-x. 0 = port not able to perform half-duplex 100base-x. r1 12 10 mbps full duplex 1 = port able to operate at 10 mbps in full-duplex mode. 0 = port not able to operate at 10 mbps full-duplex mode. r0 11 10 mbps half duplex 1 = port able to operate at 10 mbps in half-duplex mode. 0 = port not able to operate at 10 mbps in half-duplex. r1 10 100base-t2 full duplex 1 = port able to perform full-duplex 100base-t2. 0 = port not able to perform full-duplex 100base-t2. r0 9 100base-t2 half duplex 1 = port able to perform half duplex 100base-t2. 0 = port not able to perform half-duplex 100base-t2. r0 8 reserved reserved. tie to ground. r 0 7 reserved ignore when read. r 0 6 mf preamble suppression 1 = port accepts management frames with preamble suppressed. 0 = port does not accept management frames with preamble suppressed. r0 5 auto-negotiation complete 1 = auto-negotiation process completed. 0 = auto-negotiation process not completed. r0 4 remote fault 1 = remote fault condition detected. 0 = no remote fault condition detected. r/lh 0 3 auto-negotiation ability 1 = phy is able to perform auto-negotiation. 0 = phy is not able to perform auto-negotiation. r1 2 link status 1 = link is up. 0 = link is down. r/ll 0 1 reserved reserved. read as 0. r 0 0 reserved reserved. read as 0. r 0 1. r = read only; w = write only, r/w = read/write, lh = latch high, ll = latch low, sc = self clearing
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 107 6.7 phy port control registers table 70. auto-negotiation advertisement registers name size bits addr type description auto-negotiate advertisement #1 (port 1) 32 12a r see table 71 on page 107 . auto-negotiate advertisement #1 (port 2) 32 12b r auto-negotiate advertisement #1 (port 3) 32 12c r auto-negotiate advertisement #1 (port 4) 32 12d r auto-negotiate advertisement #1 (port 5) 32 12e r auto-negotiate advertisement #1 (port 6) 32 12f r auto-negotiate advertisement #1 (port 7) 32 130 r auto-negotiate advertisement #1 (port 8) 32 131 r table 71. auto negotiate advertisement bit definitions bit name description type 1 default 31.16 reserved reserved. r 0 15 next page 1 = port has ability to send multi pages. 0 = port has no ability to send multi pages. r0 14 reserved reserved. r 0 13 remote fault 1 = remote fault. 0 = no remote fault. r/w 0 12:10 reserved reserved. r 0 9 100base-t4 1 = port is 100base-t4 compatible. 0 = port is not 100base-t4 compatible. r0 8 100base-tx fd 1 = port is 100base-tx full-duplex capable. 0 = port is not 100base-tx full-duplex capable. r0 7 100base-tx 1 = port is 100base-tx capable. 0 = port is not 100base-tx capable. r/w 1 6 10base-t fd 1 = port is 10base-t fd capable. 0 = port is not 10base-t fd capable. r0 5 10base-t 1 = port is 10base-t capable. 0 = port is not 10base-t capable. r/w 1 4:0 selector field ieee 802.3. r 00001 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing table 72. phy port control register name type 1 addr description port control register r/w 132 - 139 refer to table 73 for bit assignments. 1. r = read only; w = write only; r/w = read /write.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 108 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 6.8 repeater port control/status registers the configuration register set is described in table 74 . configuration register definitions and bit assignments are shown in table 73 through table 76 . table 73. phy port control bit definitions bit name description type 1 default 31:16 reserved reserved r 0 15 reserved write as 0; ignore on read. r/w 0 14 loopback value is ? o ? only. r 0 13 speed selection 1 = 100 mbps. 0 = 10 mbps. r/w 0 12 auto-negotiation enable 1 = enable auto-negotiation process. 0 = disable auto-negotiation process. r/w 1 11 reserved write as 0; ignore on read. r/w 0 10 reserved write as 0; ignore on read. r/w 0 9 restart auto-negotiation 1 = restart auto-negotiation process. 0 = normal operation. r/w sc 0 8 duplex mode 1 = full-duplex. 0 = half-duplex. r0 7 collision test 1 = enable col signal test. 0 = disable col signal test. r/w 0 6:0 reserved write as 0, ignore on read. r/w 0000000 1. r = read only; w = write only, r/w = read/write, lh = latch high, ll = latch low, sc = self clearing table 74. configuration registers name type 1 addr description repeater configuration register r/w 13a refer to table 75 for bit assignments. repeater serial configuration register r 13b this register holds user-defined data. these bits may be used to indicate the type of board configuration, port count or other vendor-related data. default is set by pins. refer to table 76 for bit assignments. device/revision id register r 13c this register follows the ieee 1149.1 specification. refer to table 77 for bit assignments. the upper 4 bits identify the device revision level. the next 16 bits store the part id number. the next 11 bits contain a jedec manufacturer id, which for intel is hexadecimal ? fe ? . the lowest bit (0) is set only for the first device in a chain. the encoding scheme used for the product id field is implementation dependent. reserved r 13d - reserved r 13e - reserved r 13f - 1. r = read only; w = write only; r/w = read /write.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 109 global led control register r/w 140 this register reflects the led mode set by hardware pins, and provides software control for the global fault led. refer to table 78. port led control register r/w 141 this register provides a measure of software control over the port leds. refer to table 81 for bit assignments. during reset, the state of this register is all 1s. if a manager is present, this register remains in the all 1s state after reset. otherwise, the bits default to hardware control. led timer control register r/w 142 refer to ? led timer control register ? on page 112 for details. bits 15:8 of this register set the slow blink frequency of the leds. bits 7:0 set the fast blink frequency. repeater reset register w 144 writing any data value to this register with the least significant bit (lsb) = 1 causes the repeater logic to reset. (all bits other than lsb do not matter.) the counters and configuration information are held static and is not reset. refer to table 83 on page 113 for details. software reset register w 145 writing any data value to this register with the least significant bit (lsb) = 1 is identical to a hardware reset. (all bits other than lsb do not matter.) refer to table 84 on page 113 for details. assign address register (1 and 2) w 188, 189 writing a valid 48-bit id (one that matches the prom id) to this register causes the device to change its hub id to the contents of the prom id register listed below. this register cannot be read. refer to table 89 and table 90, ? assign addr 2 ? on page 116 for details. prom address register (1 and 2) r 190, 191 these two registers contain the 48-bit id read in from prom at power-up. refer to table 91 and table 92, ? prom addr 2 ? on page 116 for details. table 75. repeater configuration register bit name description type 1 default 31:15 reserved reserved - write as 0 ? s, ignore on read r/w 0 14 configuration mode select configuration mode select 0 = 2 bit direct input mode (using config[1:0]) 1 = 8 bit serial bus mode (using cfg_clk, cfg_dt, cfg_ld ) r/w 0 13 extended frame extended frame counting mode 1 = all relevant counters allow max size frames up to 1522 bytes, etherstats counter change from 1518 to 1522 0 = normal mode r/w 0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing 2. while the zeroing operation is in progress, the cpu is locked out from accessing the statistics ram until the ? zero counter ? bit has been reset back to ? 0 ? . this time period is roughly 15 s. table 74. configuration registers (continued) name type 1 addr description 1. r = read only; w = write only; r/w = read /write.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 110 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 12 enable port late event enable port late event 0 = does not allow out of window collisions to increment port late event counters. 1 = does allow out of window collisions to increment port late event counters. r/w 0 11 register clear register clear 0 = clears appropriate registers upon serial read. 1 = requires that appropriate register bits be written to be cleared. (write a ? 1 ? to the bit(s) that are to be cleared.) r/w 0 10 statistics enable statistics enable-turns statistics gathering on and off. r/w 1 9 send /t/r send /t/r - forces a good /t/r after each 100 mbps transmission r/w 0 8 isolate100 isolate100 - isolates the ir100cfs stack signal and provides an output pin for disabling an external backplane transceiver r/w 0 7 isolate10 isolate10 - same as for 100 except also isolates stack ir10colbp and ir10cfsbp signal. r/w 0 6 unicast frame count unicast frame count 1 = portreadableframes count only unicast frames. 0 = portreadableframes count all frames. r/w 0 5 arbitration value arbitration input value-as read from input pin r 0 4 zero counters zero counters 1 = lxt98x0 sequentially walks through each counter location and zero its contents. when all counter locations have been cleared, this bit is reset to ? 0 ? . 2 0 = normal r/w 0 3 enable fifo error enable fifo error 1 = lxt98x0 enters transmit collision upon detection of a data rate mismatch. 0 = normal r/w 1 2 reserved reserved - write as ? 0 ? , ignore on read. r/w 0 table 76. repeater serial configuration bit name description type 1 default 31:8 reserved reserved. r 0 7:2 rptrserconfig bits 7:2 of configuration interface data. (8-bit mode). refer to table 75 , bit 14 description. r0 1:0 rptrserconfig bits 1:0 of configuration interface data. refer to table 75, bit 14 description. r0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing table 75. repeater configuration register (continued) bit name description type 1 default 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing 2. while the zeroing operation is in progress, the cpu is locked out from accessing the statistics ram until the ? zero counter ? bit has been reset back to ? 0 ? . this time period is roughly 15 s.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 111 6.8.1 device/revision register the value of this register follows the same scheme as the device identification register found in the ieee 1149.1 specification. the upper 4 bits correspond to silicon stepping. the next 16 bits store a part id number. the next 11 bits contain a jedec manufacturer id. bit zero is ? 1 ? if the chip is the first in a stack. the encoding scheme used for the product id field is implementation dependent. 6.8.2 led control registers the led control registers and bit assignments are described in table 78 . 6.8.3 led global control register this register allows software to have a measure of control over the global fault led; it can read status of led mode. if a manager is present the default for the global fault led is 11, else it is 01. bits (5:4) state what led mode the chip is in ( ? 00 ? = mode 1, 01 ? = mode 2, ? 10 ? = mode 3 and ? 11 ? = mode 4). these bits are read-only because the led mode is set only via pins. when writing this register, all other bits in this register are reserved and may have default = 1 or 0. 6.8.4 port led control register this register (refer to table 80 ) is used to encode the measure of control software has over the port leds. the led control encodings are listed in table 81 . table 77. device/revision register bit assignment 31:28 27:12 11:8 7:1 0 version part no. jedec continuation characters jedec id 1 1st in chain 2 0000 8-port = 0010 0110 1001 1000 0000 111 1110 see note 2 6-port = 0010 0110 1000 0100 1. the jedec id is an 8-bit identifier. however, the msb is for parity only and is ignored. intel ? s jedec id is fe (1111 1110) which becomes 111 1110. 2. first chain bit = 0 if chipid 00. first chain bit = 1 if chipid = 00. table 78. global fault led bit assignments 31:6 5:4 3:2 1:0 reserved bit 31:8: write as 1; ignore on read bit 7: write as 0; ignore on read bit 6: write as 1; ignore on read mode select global fault reserved write as 0; ignore on read
lxt9860/9880 ? advanced 10/100 repeater with integrated management 112 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 6.8.5 led timer control register the upper 8 bits serves as a register for programming the slow blink frequency of the leds. the lower 8 bits program the fast led blink rate. in both registers, the maximum blink frequency is 128 hz while the minimum frequency is 0.5 hz. the slow led blink rate only applies to led mode 2, while the fast led blink rate is applicable to all led schemes. table 80. led configuration bit name description type 1 default 31:20 reserved reserved r/w 0s 19:18 mii2led see table 81 for bit definitions. r/w 10 17:16 mii1led r/w 10 15:14 portled7 r/w 10 13:12 portled6 r/w 10 11:10 portled5 r/w 10 9:8 portled4 r/w 10 7:6 portled3 r/w 10 5:4 portled2 r/w 10 3:2 portled1 r/w 10 1:0 portled0 r/w 10 1. r = read only; w = write only, r/w = read/write, lh = latch high, ll = latch low, sc = self clearing 2. during reset, the state of this register is all 1s. if a manager is present within the system, this register stays in the all 1s state following reset. otherwise, they default to hardware control (10). table 81. port led1, 2, 3 control encodings port conf. bits port led1 port led2 port led 3 modes 1, 3 and 4 function mode 2 function modes 1 and 4 function modes 2 and 3 function modes 1, 3, 4 mode 2 00 led off led off hardware control led off led off 01 reserved led fast blink reserved hardware control 10 hardware control hardware control hardware control 11 led off led on led off led off table 82. led timer control register bit assignments 31:16 15:8 7:0 reserved slow blink frequency default is xcc, 1.6 s fast blink frequency default is x32, 0.4 s period = 7.8125 ms x (register value + 1) frequency = 1 7.8125 ms x (register value + 1)
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 113 6.8.6 repeater reset register 6.8.7 software reset register 6.8.8 interrupt registers table 83. repeater reset bit name description type 1 default 31:1 reserved reserved. r 0 0 rptrrs t writing a ? 1 ? to this bit causes the repeater logic to be reset. counter and configuration logic does not reset. w0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing table 84. software reset bit name description type 1 default 31:1 reserved reserved. r 0 0swrst writing a ? 1 ? to this bit causes the chip logic to be reset. software reset is the same as a hardware reset. w0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing table 85. interrupt status/mask register name type addr description interrupt status register r/w 146 this register captures status bits within the lxt98x0 and holds them. interrupt mask register r/w 147 this register allows masking of individual interrupts.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 114 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 86. interrupt status register bit definitions bit name type 1, 2 description default 31:6 reserved r/w reserved 0 5 jabint r/w jabber interrupt a ? 1 ? indicates that a port is in jabber state. during 100 mbps operation, jabber occurs when any receiver remains active for more than 57,500 bit times. the lxt98x0 exits this state when all receivers return to the idle condition. during 10 mbps operation, jabber occurs when any port remains actively transmitting for longer than 40,000 to 75,000 bit times. the lxt98x0 asserts a minimum-ifg idle period when a port is jabbering. 0 4isolint r/w isolate interrupt a ? 1 ? indicates that a port has been isolated (100 mbps only). the lxt98x0 isolates any port transmitting more than two successive false carrier events. a false carrier event is defined as a packet not starting with a /j/k symbol pair. 0 3 partint r/w partition interrupt a ? 1 ? indicates a port has been partitioned. in 100 mbps operation, the lxt98x0 partitions any port participating in excess of 60 consecutive collisions. in 10 mbps operation, the lxt98x0 partitions any port participating in excess of 31 consecutive collisions. once partitioned, the lxt98x0 continues monitoring and transmitting to the port, but does not repeat data received from the port until it properly un-partitions. 0 2 fccint r/w false carrier count interrupt a ? 1 ? indicates a port has received too many false carrier events. 0 1sachngint r/w source address change interrupt a ? 1 ? indicates that a port address changed from that stored in the last source address register. 0 0 spdchngint r/w speed change interrupt a ? 1 ? indicates a port speed change was detected. 0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing 2. if register clear bit is set to ? 1 ? , then clearing of the associated bit is done by writing ? 1 ? to it, otherwise this register self clears upon read. register clear (bit 11) is set through the repeater configuration register. (refer to table 75 on page 109 .)
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 115 6.9 serial controller registers table 87. interrupt mask bit definitions bit name type 1 description default 31:6 reserved r/w reserved 0 5 jabmsk r/w jabber mask set 0 = do not mask 1 = mask 0 4isolmsk r/w isolate mask set 0 = do not mask 1 = mask 0 3 partmsk r/w partition mask set 0 = do not mask 1 = mask 0 2fccmsk r/w false carrier count mask set 0 = do not mask 1 = mask 0 1 sachngmsk r/w source address change mask set 0 = do not mask 1 = mask 0 0 spdchngmsk r/w speed change mask set 0 = do not mask 1 = mask 0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing. table 88. configuration registers name type 1 addr description assign address register (1 and 2) w 188, 189 writing a valid 48-bit id (one that matches the prom id) to this register causes the device to change its hub id to the contents of the prom id register listed below. this register cannot be read. refer to table 89 and table 90, ? assign addr 2 ? on page 116 for details. prom address register (1 and 2) r 190, 191 these two registers contain the 48-bit id read in from prom at power-up. refer to table 91 and table 92, ? prom addr 2 ? on page 116 for details. 1. r = read only; w = write only; r/w = read /write. table 89. assign addr 1 bit name description type 1 default 31.0 assign4716 bits (47:16) of the prom serial number w 0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing.
lxt9860/9880 ? advanced 10/100 repeater with integrated management 116 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 table 90. assign addr 2 bit name description type 1 default 31.21 reserved reserved w 0 20:16 hub id bits (4:0) of the hub id w 0 15:0 assign150 bits (15:0) of the prom serial number w 0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing. table 91. prom addr 1 bit name description type 1 default 31.0 prom4716 bits (47:16) of the prom serial number r 0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing. table 92. prom addr 2 bit name description type 1 default 31.16 reserved reserved r 0 15:0 prom150 bits (15:0) of the prom serial number r 0 1. r = read only; w = write only, r/w = read/write., lh = latch high, ll = latch low, sc = self clearing.
advanced 10/100 repeater with integrated management ? lxt9860/9880 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 117 7.0 mechanical specifications figure 42. lxt98x0 package specifications for commercial temperature e / 2 a 1 a 2 l a b l 1 3 2 d d 1 e e 1 e dim millimeters min max a - 4.10 a1 0.25 - a2 3.20 3.60 b 0.17 0.27 d 30.30 30.90 d 1 27.70 28.30 e 30.30 30.90 e 1 27.70 28.30 e .50 b asic l 0.50 0.75 l 1 1.30 ref q 0 7 2 5 16 3 5 16 208-pin plastic quad flat package part number lxt98x0hc, lxt98x0ahc commercial temperature range (0 c to 70 c)
lxt9860/9880 ? advanced 10/100 repeater with integrated management 118 datasheet document #: 248987 revision#: 003 rev date: 08/07/01 figure 43. lxt98x0 package specifications for extended temperature 208-pin plastic quad flat package heat slug part number lxt9880age extended temperature range (-40 c to +85 c)

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